NXP Semiconductors

NVT2001; NVT2002

Bidirectional voltage level translator for open-drain and push-pull applications

002aae135

A1

A2

VREFA

GND

3

4

VREFB

1

6

5

B1

B2

8 EN

SW

SW

NVT20xx

7

RPU

RPU

Vpu(D) = 3.3 V

I2C-BUS

DEVICE

SCL

SDA

VCC

GND

2

Vref(A) = 1.8 V(1)

RPU

RPU

I2C-BUS

CONTROLLER

SCL

SDA

VCC

GND

on

off

3.3 V enable signal(1)

(2)

1. In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A) should be such that Vref(B) is

at least 1 V higher than Vref(A) for best translator operation.

2. Note that the enable time and the disable time are essentially controlled by the RC time constant of the capacitor and

the 200 kΩ resistor on the EN pin.

Figure 7. Typical application circuit (switch enable control)

EN

VREFB

002aae133

B1

B2

CHIPSET I/O

VCC

5 V

totem pole or

open-drain I/O

GND

VREFA

A1

A2

B3

VCC

Bn

3.3 V

A3

An

CPU I/O

VCORE

1.8 V

1.5 V

1.2 V

1.0 V

SW

NVT20xx

SW

SW

CHIPSET I/O

SW

B4

A4

B5

A5 SW

SW

B6

A6

SW

Figure 8. Bidirectional translation to multiple higher voltage levels

NVT2001_NVT2002

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© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 4.4 — 22 May 2023

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