EN27C010
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
3
FIGURE 4. BLOCK DIAGRAM
CE
PGM
OE
A0-A16
ADDRESS
INPUTS
CONTROL
LOGIC
VCC
VSS
VPP
INPUT/
OUTPUT
BUFFERS
DQ0 - DQ7
8
8
1024
Y-DECODER
Y-SELECT
X-DECODER
1M BIT
CELL
MATRIX
1024
FUNCTIONAL DESCRIPTION
THE QUIKRITE
TM PROGRAMMING OF THE EN27C010
When
the
EN27C010
is
delivered,
the
chip
has
all
1M
bits
in
the
“ONE”,
or
HIGH state. “ZEROs” are loaded into the EN27C010 through the procedure of programming.
The programming mode is entered when 12.75
± 0.25V is applied to the VPP pin, OE is at VIH,
and
CE and PGM are at VIL. For programming, the data to be programmed is applied with 8
bits in parallel to the data pins.
The QUIKRITE
TM
programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20
µs to 100 µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27C010. This part of the programming algorithm is done at
VCC = 6.25V to assure that each EPROM bit is programmed to a sufficiently high threshold
voltage. This ensures that all bits have sufficient margin. After the final address is completed,
the entire EPROM memory is read at VCC = VPP = 5.25 ± 0.25V to verify the entire memory.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
