AM29F800T datasheet(17/41 Pages) AMD

17 / 41 page

8/18/97

Am29F800T/Am29F800B

PR E L IM IN A R Y

cause DQ6 to toggle. See Figure 12 for the Toggle Bit

timing specifications and diagrams.

DQ5: Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count).

Under these conditions DQ5 will produce a “1”. This is

a failure condition which indicates that the program or

erase cycle was not successfully completed. Data Poll-

ing is the only operating function of the device under

this condition. The CE circuit will partially power down

the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output dis-

able functions as described in Table 1.

The DQ5 failure condition will also appear if a user tries

to program a 1 to a location that is previously pro-

grammed to 0. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system never reads a valid data on DQ7 bit

and DQ6 never stops toggling. Once the device has ex-

ceeded timing limits, the DQ5 bit will indicate a “1”.

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs,

reset the device.

DQ3: Sector Erase Timer

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

DQ3 will remain low until the time-out is complete. Data

Polling and Toggle Bit are valid after the initial sector

erase command sequence.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, DQ3 may be

used to determine if the sector erase timer window is

still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent

commands (other than Erase Suspend) to the device

will be ignored until the erase operation is completed

as indicated by Data Polling or Toggle Bit. If DQ3 is low

(“0”), the device will accept additional sector erase

commands. To insure the command has been ac-

cepted, the system software should check the status of

DQ3 prior to and following each subsequent sector

erase command. If DQ3 were high on the second sta-

tus check, the command may not have been accepted.

Refer to Table 8, Hardware Sequence Flags.

DQ2: Toggle Bit 2

This toggle bit, along with DQ6, can be used to deter-

mi ne w h eth e r th e de v ic e i s i n the E m bed de d

Erase Algorithm or in Erase suspend.

Successive reads from the erasing sector will cause

DQ2 to toggle during the Embedded Erase Algorithm.

If the device is in the erase suspend-read mode, suc-

cessive reads from the erase-suspend sector will

cause DQ2 to toggle. When the device is in the erase

suspend-program mode, successive reads from the

byte address of the non-erase suspend sector will indi-

cate a logic “1” at the DQ2 bit. Note that a sector which

is selected for erase is not available for read in Erase

Suspend mode. Other sectors which are not selected

for Erase can be read in Erase Suspend.

DQ6 is different from DQ2 in that DQ6 toggles only

when the standard program or erase, or erase sus-

pend-program operation is in progress.

If the DQ5 failure condition is observed while in Sector

Erase mode (i.e., exceeded timing limits), the DQ2 tog-

gle bit can give extra information. In this case, the nor-

mal function of DQ2 is modified. If DQ5 is at logic “1”,

then DQ2 will toggle with consecutive reads only at the

sector address that caused the failure condition. DQ2

will toggle at the sector address where the failure oc-

curred and will not toggle at other sector addresses.

RY/BY: Ready/Busy

The Am29F800 provides a RY/BY open-drain output

pin as a way to indicate to the host system that the Em-

bedded Algorithms are either in progress or have been

completed. If the output is low, the device is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operation. When the RY/BY pin is low, the device

will not accept any additional program or erase com-

mands with the exception of the Erase Suspend com-

mand. If the Am29F800 is placed in an Erase Suspend

mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after

the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse. The RY/BY pin should be

ignored while RESET is at VIL. Refer to Figure 13 for a

detailed timing diagram.

Since this is an open-drain output, several RY/BY

pins can be tied together in parallel with a pull-up resis-

tor to VCC.

RESET: Hardware Reset

The Am29F800 device may be reset by driving the

RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will

be terminated and the internal state machine will be

reset to the read mode 20

µs after the RESET pin is

driven low. Furthermore, once the RESET pin goes

high, the device requires an additional 50 ns before it

will allow read access. When the RESET pin is low, the

device will be in the standby mode for the duration of

the pulse and all the data output pins will be tri-stated.

If a hardware reset occurs during a program or erase

operation, the data at that particular location will

be indeterminate.

The RESET pin may be tied to the system reset input.

Therefore, i f a s y st em res e t oc c u rs during

the Embedded Program or Erase Algorithm, the device

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