AM29F800T datasheet(18/41 Pages) AMD

18 / 41 page

Am29F800T/Am29F800B

8/18/97

PR E L IM IN A R Y

will be automatically reset to read mode and this will

enable the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word

(16 bit) mode for the Am29F800 device. When this pin is

driven high, the device operates in the word (16 bit)

mode. The data is read and programmed at DQ0–

DQ15. When this pin is driven low, the device operates

in byte (8 bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ8–DQ14 bits are

tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at

DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer

to Figures 15 and 16 for the timing diagram.

Data Protection

The Am29F800 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power tran-

sitions. During power up the device automatically re-

sets the internal state machine in the Read mode. Also,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific multi-bus cycle command sequences.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting from VCC

power-up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, the Am29F800 locks out write cycles

for VCC < VLKO (see DC Characteristics section for volt-

ages). When VCC < VLKO, the command register

is disabled, all internal program/erase circuits are dis-

abled, and the device resets to the read mode. The

Am29F800 ignores all writes until VCC > VLKO. The

user must ensure that the control pins are in the correct

logic state when VCC > VLKO to prevent unintentional

writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,

CE = VIH, or WE = VIH. To initiate a write cycle CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and

OE = VIH will not accept commands on the rising edge

of WE. The internal state machine is automatically

reset to the read mode on power-up.

AM29F800T Datasheet(PDF) 18 Page - Advanced Micro Devices

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