AD5398 datasheet(3/16 Pages) AD

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AD5398

Rev. A | Page 3 of 16

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX,

unless otherwise noted.

Table 1.

B Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DC PERFORMANCE

VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with

reduced performance

Resolution

Bits

117 μA/LSB

Relative Accuracy2

±1.5

±4

LSB

Differential Nonlinearity2, 3

±1

LSB

Guaranteed monotonic over all codes

Zero Code Error2, 4

All 0s loaded to DAC

Offset Error @ Code 162

0.5

Gain Error2

±0.6

% of FSR

@ 25°C

Offset Error Drift4, 5

μA/ºC

Gain Error Drift2, 5

±0.2

±0.5

LSB/ºC

OUTPUT CHARACTERISTICS

Minimum Sink Current4

Maximum Sink Current

120

VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V but

specified maximum sink current might not be achieved

Output Current During PD

PD = 1

Output Compliance5

0.6

VDD

Output voltage range over which max sink current is

available

Power-Up Time

μs

To 10% of FS, coming out of power-down mode; VDD = 5 V

LOGIC INPUTS (PD)5

Input Current

±1

μA

Input Low Voltage, VINL

0.8

VDD = 2.7 V to 5.5 V

Input High Voltage, VINH

0.7 VDD

VDD = 2.7 V to 5.5 V

Pin Capacitance

LOGIC INPUTS (SCL, SDA)5

Input Low Voltage, VINL

−0.3

0.3 VDD

Input High Voltage, VINH

0.7 VDD

VDD + 0.3

Input Leakage Current IIN

±1

μA

VIN = 0 V to VDD

Input Hysteresis, VHYST

0.05 VDD

Digital Input Capacitance, CIN

Glitch Rejection6

Pulse width of spike suppressed

POWER REQUIREMENTS

VDD

2.7

5.5

IDD (Normal Mode)

IDD specification is valid for all DAC codes.

VDD = 2.7 V to 5.5 V

VDD = 2.7 V to 4.5 V

2.5

2.3

VIH = VDD, VIL = GND, VDD = 5.5 V

VIH = VDD, VIL = GND, VDD = 4.5 V

IDD (Power-Down Mode)

0.5

μA

VIH = VDD, VIL = GND

1 Temperature range is as follows: B Version: –40°C to +85°C.

2 See the Terminology section.

3 Linearity is tested using a reduced code range: Codes 32 to 1023.

4 To achieve near zero output current, use the power-down feature.

5 Guaranteed by design and characterization; not production tested.

6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

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