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P25Q32SL Datasheet(PDF) 92 Page - Puya Semiconductor Co., Ltd.

Part # P25Q32SL
Description  Ultra Low Power, 32M-bit Serial Multi I/O Flash Memory Datasheet
PDF  111 Pages
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Manufacturer  PUYA [Puya Semiconductor Co., Ltd.]
Direct Link  http://www.puyasemi.com/index_en.html
Logo PUYA - Puya Semiconductor Co., Ltd.

P25Q32SL Datasheet(HTML) 92 Page - Puya Semiconductor Co., Ltd.

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P25Q32SL Datasheet
Puya Semiconductor
Page 92 of 111
10.54 Global Block Lock (GBLK)
The GBLK instruction is for enable the lock protection block of the whole chip. The WREN (Write Enable)
instruction is required before issuing GBLK instruction.
The sequence of issuing GBLK instruction is: CS# goes low → send GBLK (7Eh) instruction →CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't
care" in SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be
executed.
Figure 10-53 Global Block Lock(Command 7EH)
Command
0
1
2
3
4
5
6
7
7EH
CS#
SCLK
SI
SO
High-Z
Figure 10-53a Global Block Lock(QPI)
CS#
SCLK
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Command
7EH
0
1



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