P25Q32SL datasheet(34/111 Pages) PUYA

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P25Q32SL Datasheet

Puya Semiconductor

Page 34 of 111

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4-BP0

bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details.

The default setting is CMP=0.

SUS bit

The SUS bit is read only bit in the status register (S15) that is set to 1 after executing an Program/Erase

Suspend (75H) command. The SUS bit is cleared to 0 by Program/Erase Resume (7AH) command as well as

a power-down, power-up cycle.

10.6 Read Configure Register (RDCR)

The RDCR instruction is for reading Configure Register Bits. The Read Configure Register can be read at any

time (even in program/erase/write status register condition). It is recommended to check the Write in Progress

(WIP) bit before sending a new instruction when a program, erase, or write status register operation is in

progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configure

Figure 10-6 Read Status Register (RDCR) Sequence (Command 15)

Command

10 11 12 13 14 15 16 17 18 19 20 21 22 23

15H

CS#

SCLK

High-Z

MSB

Configure Register Out

MSB

Figure 10-6a Read Status Register (RDCR) Sequence (QPI)

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

Command

15H

C7-C0 out

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