AD7982 datasheet(13/23 Pages) AD

13 / 23 page

Preliminary Technical Data

AD7982

Rev PrC | Page 13 of 23

SINGLE-TO-DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either

bipolar or unipolar, the ADA4941 single-ended-to-differential

driver allows for a differential input into the part. The

schematic is shown in Figure 15.

R1, R2 set the attenuation ratio between the input range and the

ADC range (VREF). R1, R2 and CF shall be chosen depending on

the desired input resistance, signal bandwidth, anti-aliasing and

noise contribution.

– e.g.: for +/-10V range with 4k Ω impedance, R2=1k Ω and

R1= 4k Ω

R3, R4 and R5, R6 set the common mode on, respectively, the

IN- and IN+ inputs of the ADC which should be close to

VREF/2.

– e.g.: for +/-10V range with single supply, R3=8.45k Ω, R4=

11.8k Ω and R5=10.5kΩ, R6= 9.76kΩ

AD7982

μF

5V REF

REF

GND

IN+

IN–

ADA4941

±10V, ±5V, ..

100nF

2.7nF

VDD

5.2V

2.5V

100nF

-0.2V

Figure 15. Single-Ended-to-Differential Driver Circuit

VOLTAGE REFERENCE INPUT

The AD7982 voltage reference input, REF, has a dynamic, input

impedance and should therefore be driven by a low impedance

source with efficient decoupling between the REF and GND

pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for

example, a reference buffer using the AD8031 or the AD8605, a

10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for

optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

If desired, smaller reference decoupling capacitor values down

to 2.2 μF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value

ceramic decoupling capacitor (for example, 100 nF) between the

REF and GND pins.

POWER SUPPLY

It uses two power supply pins: a core supply VDD and a digital

input/output interface supply VIO. VIO allows direct interface

with any logic between 1.8 V and VDD. To reduce the supplies

needed, the VIO and VDD can be tied together. The AD7982 is

independent of power supply sequencing between VIO and

VDD. Additionally, it is very insensitive to power supply

variations over a wide frequency range.

To ensure optimum performance, VDD should be roughly half

of REF, the voltage reference input. For example if REF is 5.0V,

VDD should be set to 2.5V (+/-5%).

The AD7982 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate. This makes the part ideal for low sampling

rate (even a few Hz) and low battery-powered applications.

AD7982 Datasheet(PDF) 13 Page - Analog Devices

AD7982 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL