AD7982 datasheet(17/23 Pages) AD

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Preliminary Technical Data

AD7982

Rev PrC | Page 17 of 23

CS Mode 4-Wire, No BUSY Indicator

This mode is usually used when multiple AD7982s are

connected to an SPI compatible digital host.

A connection diagram example using two AD7982s is shown in

Figure 20 and the corresponding timing is given in Figure 21.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI could

be used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time and held high until the maximum conversion time to

avoid the generation of the BUSY signal indicator. When the

conversion is complete, the AD7982 enters the acquisition

phase and powers down. Each ADC result can be read by

bringing low its SDI input which consequently outputs the MSB

onto SDO. The remaining data bits are then clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge will allow a faster

reading rate provided it has an acceptable hold time. After the

18th SCK falling edge, or when SDI goes high, whichever is

earlier, SDO returns to high impedance and another AD7982

can be read.

CNV

SCK

SDO

SDI

DATA IN

CLK

CS1

CONVERT

CS2

DIGITAL HOST

CNV

SCK

SDO

SDI

AD7982

Figure 20. CS Mode 4-Wire, No BUSY Indicator Connection Diagram

SDO

D17

D16

D15

tDIS

SCK

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI(CS1)

CNV

tSSDICNV

tHSDICNV

tSCK

tSCKL

tSCKH

D17

D16

SDI(CS2)

Figure 21. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing

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