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MC68340 Datasheet(PDF) 354 Page - Freescale Semiconductor, Inc |
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MC68340 Datasheet(HTML) 354 Page - Freescale Semiconductor, Inc |
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354 / 441 page ![]() 8- 10 MC68340 USER’S MANUAL MOTOROLA successive timeout causes the counter to be loaded alternately with the values from PREL1 and PREL2. TOUTx behaves as a variable duty-cycle square wave when the CR OC bits are programmed for toggle mode. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUTx. The third timeout occurs after N1 + 1 periods, resulting in a change of state on TOUTx, and so on (see Figure 8-6). The OUT bit in the SR reflects the level of TOUTx. COUNTER CLOCK 0 0 4 3 2 1 0 2 1 0 4 3 2 1 COUNTER TOUT N1: N1 + 1 N2 + 1 N1 + 1 ENABLE TIMEOUT TIMEOUT TIMEOUT MODEx Bits in Control Register = 010 Preload 1 Register = N1 = 4 Preload 2 Register = N2 = 2 OCx Bits in Control Register = 01 0 2 1 0 TIMEOUT N2 + 1 Figure 8-6. Variable Duty-Cycle Square-Wave Generator Mode If TGATE ≈ is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the TG bit of the SR is set, indicating that TGATE ≈ was negated. The ON bit of the SR is cleared, indicating that the timer is disabled. If TGATE ≈ is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE ≈ was negated. The ON bit is set again. If TGATE ≈ is not enabled (TGE = 0), TGATE≈ has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE ≈. The duty cycle of the waveform generated on TOUTx can be dynamically changed by writing new values into PREL1 and/or PREL2. If PREL1 or PREL2 is being accessed simultaneously by the counter logic and a CPU32 write, the old preload value may actually get loaded into the counter at timeout. If at timeout, the counting logic was accessing PREL2 and the CPU32 was writing to PREL1 (or visa versa), there would be no unexpected results. 8.3.4 Variable-Width Single-Shot Pulse Generator This mode is used to produce a one-time pulse that has a delay controlled by the value stored in PREL1 and a duration controlled by the value stored in PREL2. With TOUTx programmed to change state, this sequence creates a single pulse of variable width. This mode can be selected by programming the CR MODE bits to 011. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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