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MC68340 Datasheet(PDF) 409 Page - Freescale Semiconductor, Inc |
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MC68340 Datasheet(HTML) 409 Page - Freescale Semiconductor, Inc |
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409 / 441 page  MOTOROLA MC68340 USER’S MANUAL 11-9 11.7 AC TIMING SPECIFICATIONS (Continued) 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Num. Characteristic Symbol Min Max Min Max Min Max Unit 304 CLKOUT Low to Data-In Invalid (Fast Termination Hold) tCLDI 30 — 15 — 10 — ns 30A4 CLKOUT Low to Data-In High Impendance tCLDH — 180 — 90 — 60 ns 315 DSACK ≈ Asserted to Data-In Valid tDADI — 100 — 50 — 32 ns 31A DSACK ≈ Asserted to DSACK≈ Valid (Skew) tDADV — 60 — 30 — 20 ns 32 HALT and RESET Input Transition Time tHRrf — 400 — 200 — 140 ns 33 CLKOUT Low to BG Asserted tCLBA — 60 — 30 — 20 ns 34 CLKOUT Low to BG Negated tCLBN — 60 — 30 — 20 ns 356 BR Asserted to BG Asserted (RMC Not Asserted) tBRAGA 1 — 1 — 1 — CLKOUT 37 BGACK Asserted to BG Negated tGAGN 1 2.5 1 2.5 1 2.5 CLKOUT 39 BG Width Negated tGH 2 —2—2— CLKOUT 39A BG Width Asserted tGA 1 —1—1— CLKOUT 46 R/ W Width Asserted (Write or Read) tRWA 300 — 150 — 100 — ns 46A R/ W Width Asserted (Fast Termination Write or Read) tRWAS 180 — 90 — 60 — ns 47A8 Asynchronous Input Setup Time tAIST 15 — 8, 5 — 5 — ns 47B Asynchronous Input Hold Time tAIHT 30 — 15 — 10 — ns 485,7 DSACK ≈ Asserted to BERR, HALT Asserted tDABA — 60 — 30 — 20 ns 53 Data-Out Hold from CLKOUT High tDOCH 0 —0—0— ns 54 CLKOUT High to Data-Out High Impedance tCHDH — 60 — 30 — 20 ns 55 R/ W Asserted to Data Bus Impedance Change tRADC 80 — 40 — 25 — ns 56 RESET Pulse Width (Reset Instruction) tHRPW 512 — 512 — 512 — CLKOUT 56A RESET Pulse Width (Input from External Device) tRPWI 590 — 590 — 590 — CLKOUT 57 BERR Negated to HALT Negated (Rerun) tBNHN 0 —0—0— ns 70 CLKOUT Low to Data Bus Driven (Show Cycle) tSCLDD 0 60 0 30 0 20 ns 71 Data Setup Time to CLKOUT Low (Show Cycle) tSCLDS 30 — 15 — 10 — ns 72 Data Hold from CLKOUT Low (Show Cycle) tSCLDH 20 — 10 —6— ns 80 DSI Input Setup Time tDSISU 30 — 15 — 10 — ns 81 DSI Input Hold Time tDSIH 20 — 10 —6— ns 82 DSCLK Setup Time tDSCSU 30 — 15 — 10 — ns 83 DSCLK Hold Time tDSCH 20 — 10 —6— ns 84 DSO Delay Time tDSOD — tcyc + 50 — tcyc + 25 — tcyc + 16 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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