MC68340 datasheet(406/441 Pages) FREESCALE

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11-6

MC68340 USER’S MANUAL

MOTOROLA

11.6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING (See notes (a), (b),

(c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70

°C; see numbered notes)

3.3 V

3.3 V or 5.0 V

5.0 V

8.39 MHz

16.78 MHz

25.16 MHz

Num.

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

System Frequency1

fsys

8.39

16.78

25.16

MHz

Crystal Frequency

fXTAL

kHz

On-Chip VCO System Frequency

fsys

0.13

8.39

0.13

16.78

0.13

25.16

MHz

On-Chip VCO Frequency Range

fVCO

0.1

16.78

0.1

33.5

0.1

50.3

MHz

External Clock Operation

fsys

MHz

PLL Start-up Time2

trc

—

Limp Mode Clock Frequency 3

SYNCR X-bit = 0

SYNCR X-bit = 1

flimp

—

fsys/2

fsys

—

fsys/2

fsys

—

fsys/2

fsys

kHz

CLKOUT stability 4

∆CLK

–1

CLKOUT Period in Crystal Mode

tcyc

119.2

—

59.6

—

1B6

External Clock Input Period

tEXTcyc

125

—

62.5

—

1C 7

External Clock Input Period with PLL

tEXTcyc

125

—

62.5

—

2,3 8

CLKOUT Pulse Width in Crystal Mode

tCW

—

2B, 3B9 CLKOUT Pulse Width in External Mode

tEXTCW

—

2C,

3C 10

CLKOUT Pulse Width in External w/PLL

Mode

tEXTCW

62.5

—

4,5

CLKOUT Rise and Fall Times

tCrf

—

NOTES:

(a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V

±0.3 V are preliminary

and apply only to the appropriate MC68340V low voltage part.

(b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V

±5% operation.

±5% electrical specifications are preliminary.

(d) For extended temperature parts T A = –40 to +85°C. These specifications are preliminary.

All internal registers retain data at 0 Hz.

Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 µF is attached to

the XFC pin, and that the crystal oscillator is stable. Lock time is measured from power-up to

RESET release.

This specification also applies to the period required for PLL lock after changing the W and Y frequency control

bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock

to lock after LPSTOP.

Determined by the initial control voltage applied to the on-chip VCO. The X-bit in the SYNCR controls a divide -

by-two scaler on the system clock output.

CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys.

Measurement is made with a stable external clock input applied using the PLL.

All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input.

When using the external clock input mode (MODCK reset value = 0 V), the minimum allowable t EXTcyc period

will be reduced when the duty cycle of the signal applied to EXTAL exceeds 5% tolerance. The relationship

between external clock input duty cycle and minimum t EXTcyc is expressed:

Minimum tEXTcyc period = minimum tEXTCW / (50% – external clock input duty cycle tolerance).

Minimum external clock low and high times are based on a 45% duty cycle.

When using the external clock input mode with the PLL (MODCK reset value = 0 V), the external clock input duty

cycle can be at minimum 20% to produce a CLKOUT with a 50% duty cycle.

For crystal mode operation, the minimum CLKOUT pulse width is based on a 47% duty cycle.

For external clock mode operation, the minimum CLKOUT pulse width is based on a 45% duty cycle, with a 50%

duty cycle input clock.

Freescale Semiconductor, Inc.

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