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MC68340 Datasheet(PDF) 408 Page - Freescale Semiconductor, Inc |
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MC68340 Datasheet(HTML) 408 Page - Freescale Semiconductor, Inc |
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408 / 441 page  11-8 MC68340 USER’S MANUAL MOTOROLA 11.7 AC TIMING SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70 °C; see numbered notes; see Figures 11-2–11-11) 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Num. Characteristic Symbol Min Max Min Max Min Max Unit 6 CLKOUT High to Address, FC, SIZ, RMC Valid tCHAV 060 030 020 ns 7 CLKOUT High to Address, Data, FC, SIZ, RMC High Impedance tCHAZx 0 120 0 60 0 40 ns 8 CLKOUT High to Address, FC, SIZ, RMC Invalid tCHAZn 0 — 0 — 0 — ns 99 CLKOUT Low to AS, DS, CS, IFETCH, IPIPE, IACK ≈ Asserted tCLSA 3 60 3 30 3 20 ns 9A2 AS to DS or CS Asserted (Read) tSTSA –30 30 –15 15 –6 6 ns 11 Address, FC, SIZ, RMC Valid to AS, CS (and DS Read) Asserted tAVSA 30 — 15 — 10 — ns 12 CLKOUT Low to AS, DS, CS, IFETCH, IPIPE, IACK ≈ Negated tCLSN 3 60 3 30 3 20 ns 13 AS, DS, CS, IACK ≈ Negated to Address, FC, SIZ Invalid (Address Hold) tSNAI 30 — 15 — 10 — ns 14 AS, CS (and DS Read) Width Asserted tSWA 200 — 100 — 70 — ns 14A DS Width Asserted (Write) tSWAW 90 — 45 — 30 — ns 14B AS, CS, IACK ≈ (and DS Read) Width Asserted (Fast Termination Cycle) tSWDW 80 — 40 — 30 — ns 153 AS, DS, CS Width Negated tSN 80 — 40 — 30 — ns 16 CLKOUT High to AS, DS, R/ W High Impedance tCHSZ — 120 — 60 — 40 ns 17 AS, DS, CS Negated to R/W High tSNRN 30 — 15 — 10 — ns 18 CLKOUT High to R/ W High tCHRH 060 030 020 ns 20 CLKOUT High to R/ W Low tCHRL 060 030 020 ns 219 R/ W High to AS, CS Asserted tRAAA 30 — 15 — 10 — ns 22 R/ W Low to DS Asserted (Write) tRASA 140 — 70 — 47 — ns 23 CLKOUT High to Data-Out Valid tCHDO —60 —30 —20 ns 24 Data-Out Valid to Negating Edge of AS, CS, (Fast Termination Write) tDVASN 30 — 15 — 10 — ns 25 DS, CS, Negated to Data-Out Invalid (Data-Out Hold) tSNDOI 30 — 15 — 10 — ns 26 Data-Out Valid to DS Asserted (Write) tDVSA 30 — 15 — 10 — ns 27 Data-In Valid to CLKOUT Low (Data Setup) tDICL 10 —5—5— ns 27A Late BERR, HALT, BKPT Asserted to CLKOUT Low (Setup Time) tBELCL 40 — 20 — 10 — ns 28 AS, DS Negated to DSACK ≈, BERR, HALT Negated tSNDN 0 160 0 80 0 50 ns 294 DS, CS Negated to Data-In Invalid (Data-In Hold) tSNDI 0 — 0 — 0 — ns 29A4 DS, CS Negated to Data-In High Impedance tSHDI — 120 — 60 — 40 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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