MC68340 datasheet(438/441 Pages) FREESCALE

438 / 441 page

Index-6

MC68340 USER’S MANUAL

MOTOROLA

Pin Assignment Register 1, 4-15, 4-33, 4-37

Pin Assignment Register 2, 4-15, 4-34, 4-37

Pins

Functions, 4-15

Assignment Encoding, 4-15, 4-34

Port B

Configuration, 4-5, 4-16

Data Direction Register, 4-35

Data Register, 4-35

Functions, 4-16

Pin Assignment Register, 4-16, 4-35, 4-37

Pins

Functions, 2-6, 2-9, 4-16

Pin Assignment Encoding, 4-16, 4-35

Port Size, 4-14, 6-31

Port Width, 3-1, 3-7

POT Bits, 8-22, 8-28

Power Considerations, 11-2

Power Consumption, 1-8–1-9, 10-11

Power Dissipation, 10-11

Prefetch Controller, 5-90–5-91

Prefetch Faults, 5-55–5-58, 5-62

Preload Register 1, 8-6–8-13, 8-25–8-27

Preload Register 2, 8-10–8-11, 8-13, 8-26–8-27

Privilege Violations, 5-48

Processor Clock Circuitry, 10-1–10-2

Program Control Instructions, 5-26–5-27

Program Counter, 5-6, 5-67–5-68

Programming Model

CPU32, 5-8–5-9

DMA, 6-23

Serial, 7-19

SIM40, 4-19

Timer, 8-18

Propagation Delays, 10-7

PS Bits, 4-14, 4-32

PT Bit, 7-23, 7-47

PTP Bit, 4-7, 4-27, 4-37

Pulse-Width Measurement, 8-12–8-13

Pulse-Width Modulation, 8-6–8-7

— R —

R/F Bit, 7-22, 7-47

R/W Field, 5-73

RB Bit, 7-13, 7-24, 7-30

RC Bits, 7-30

RCS Bits, 7-26

Read

A/D Register Command, 5-76–5-77

Cycle Word Read, Flowchart, 3-16

Memory Location Command, 5-79–5-80

Modify Write Cycle, 5-53

Modify Write Faults, 5-55–5-56, 5-58

System Register Command, 5-67, 5-77–5-78

Read-Modify-Write Cycle Timing, 3-19

Retry Operation, 3-36

Interruption, 3-36, 3-43

Operation, 3-4

Read-Modify-Write Signal, 2-8, 3-19–3-21, 3-40,

3-42–3-43, 3-45

Read/Write Signal, 2-7, 3-2

Real-Time Clock, 4-9

Receive Data Signal, 2-11

Received Break, 7-11, 7-24, 7-33

Receiver, 7-9, 7-11

Baud Rates, 7-26

Buffer, 7-11–7-12, 7-25, 7-30

Disable Command, 7-30

Enable Command, 7-30

FIFO, 7-12–7-13, 7-17, 7-22–7-23, 7-25, 7-33–7-34

Holding Registers, 7-9, 7-11

Ready Signal, 2-12

Shift Register, 7-9, 7-12

Timing, 7-12

Field, 5-74

Indirect Addressing Mode, 5-5

Released Write, 5-57

Remote Loopback Mode, 7-14, 7-38

REQ Bits, 6-27, 6-29, 6-37

Request to Send Signal, 2-11

Reset

Break-Change Interrupt, 7-28

Effect on DMA Transfers, 6-20

Error Status Command, 7-28

Exception, 5-43–5-44

Instruction, 5-85

Peripherals Command, 5-85–5-86

Operation, 3-45, 3-46

Receiver Command, 7-28

Signal, 2-8, 3-45–3-48, 5-66

Status Register, 4-3, 4-23

Types, 3-45

Timing, 3-47

Transmitter Command, 7-28

Values for Counter and Prescaler, 8-2

Vector, 5-4

RESET Signal, 3-45–3-48, 5-43

Retry Bus Cycle Operation, 3-32, 3-34–3-35

Timing, 3-37

Timing, Late Retry, 3-38

Return From Exception, 5-51–5-52

Return Program Counter, 5-67–5-68

Returning From Background Mode, 5-68

RM Bit, 5-53

ROM Interface, 10-3

RR Bit, 5-53

RS-232 Interface, 10-4–10-5

RSTEN Bit, 4-29

RTE Instruction, 5-57–5-59, 5-61

RTS Operation, 7-11, 7-22

RTSA Signal, 7-6, 7-37

RTSB Signal, 7-6, 7-36

RTS

≈ Signal, 7-11, 7-13, 7-22, 7-29, 7-38

RW Bit, 5-54

RxDx Signal, 7-6, 7-11, 7-14, 7-24

RxRDA Bit, 7-11, 7-13, 7-15, 7-24, 7-25

RxRDYA Bit, 7-34–7-35

Freescale Semiconductor, Inc.

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