MC68340 datasheet(439/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

Index-7

≈RDYA Signal, 7-7, 7-36

RxRDYB Bit, 7-33, 7-35

RxRTS Bit, 7-22, 7-47

— S —

S/D Bit, 6-30, 6-37

SAPI Bits, 6-12, 6-19, 6-28, 6-37

Save and Restore Operations Timing Table, 5-113

SB Bits, 7-39, 7-47

SCLK Signal, 7-3, 7-6, 7-8, 7-20

SE Bit, 6-25, 6-36

Selected Clock, 8-3, 8-21

Serial

Clock Signal, 2-11

Command Control, 7-27

Communication Overview, 7-3

Compatibility with MC68681, 7-4

Crystal Oscillator, 7-3, 7-5

Diagnostic Functions, 7-14

Initialization, 7-46–7-49

Interface Timing, 5-68–5-71

Interface, 10-4–10-5

Maximum Data Transfer Rate, 7-2

Module Capabilities, 7-2

Module Programming Model, 7-19

Module Programming, 7-40

State Machine, 5-69–5-71

SFC Bits, 6-32

Shadowing, 8-6–8-7

SHEN Bits, 4-5, 4-22

Shift and Rotate

Instructions, 5-24–5-25

Instruction Timing Table, 5-108

Show Cycles, 4-3, 4-22

Operation, 3-42–3-43, 3-45

Signal Relationships to CLKOUT, 10-7

Signal Widths, 10-8

SIM40

Configuration, 4-3

Programming Model, 4-19

Simultaneous Interrupts, 4-9

Single Address

Mode, 6-2, 6-6–6-7, 6-10, 6-19, 6-27, 6-37

Source Read, 6-7–6-8

Source Write, 6-10–6-11

Single Operand Instruction Timing Table, 5-107

Single Step Operation, 3-36

Six-Word Stack Frame, 5-52, 5-60

SIZ Bits, 5-56–5-57, 5-73

Size

Signal Encoding, 2-7, 3-3

Signals, 2-7, 3-3, 3-5–3-7

Skew Between Outputs, 10-9

Slave Station, 7-15

SLIMP Bit, 4-11, 4-29

SLOCK, 4-11, 4-29

Software

Breakpoints, 5-53–5-54

Interrupt Vector Register, 4-7, 4-24, 4-36

Operation, 4-4, 4-6, 4-17, 4-27

Service Register, 4-7, 4-28

Service Routine, 4-7, 4-25

Timeout, 4-25

Watchdog, 4-1, 4-4, 4-6

Watchdog Clock Rate, 4-7

Source Address Register, 6-7, 6-12, 6-18–6-19,

6-28, 6-33, 6-37, 6-38

Special Status Word, 5-45, 5-52

Special-Purpose MOVE Instruction Timing Table,

5-101–5-102

Spurious Interrupt, 3-29

Monitor, 4-1, 4-4, 4-6, 4-17,

Square-Wave Generation, 8-6, 8-8–8-9

SRAM Interface, 10-3

SSIZE Bits, 6-12, 6-19, 6-29, 6-37

Stack

Frames, 5-60–5-63

Pointer, 5-60–5-63

Start Break Command, 7-29

Status Register, 5-57, 5-59–5-60, 5-62–5-63, 7-10,

7-11, 7-24, 8-2, 8-4, 8-23–8-25

STEXT Bit, 4-13, 4-17, 4-29, 4-36

Stop Bit, 7-11

Length, 7-39

Stop Break Command, 7-29

STOP Instruction, 4-17

Stop Module Operation, 6-24, 7-20, 8-19

Stopped Processing State, 5-37

STP Bit, 4-17, 6-24, 6-36, 7-20, 7-46, 8-19,

STR Bit, 6-3, 6-4, 6-5, 6-19, 6-30, 6-35, 6-37–6-38

STSIM Bit, 4-13, 4-17, 4-29, 4-36

Supervisor Privilege Level, 3-3

SUPV Bit, 4-22, 6-22, 6-25, 6-36, 7-21, 7-46, 8-19,

8-27

Surface Interpolation with Tables, 5-29–5-36

SW Bit, 4-23

SWE Bit, 4-6, 4=24, 4-37

SWP Bit, 4-7, 4-25, 4-27, 4-37

SWR Bit, 8-6, 8-8, 8-13, 8-20, 8-27

SWRI Bit, 4-7, 4-24, 4-37

SWT Bits, 4-7, 4-25, 4-37

Synchronous

Accesses, 3-4

Operation, 3-14

System

Clock, 8-3

Configuration and Protection, 4-1, 4-3, 4-6

Control Instructions, 5-27–5-28

Protection and Control Register, 4-6, 4-24, 4-37

— T —

Table Lookup and Interpolate Instructions, 5-7,

5-12, 5-29–5-36

TAP Controller, 9-2–9-3

TC Bits, 8-7, 8-24

TCK Signal, 2-13, 9-2, 9-11, 9-12

Freescale Semiconductor, Inc.

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