MC68340 datasheet(440/441 Pages) FREESCALE

440 / 441 page

Index-8

MC68340 USER’S MANUAL

MOTOROLA

TCS Bits, 7-27

TDI Signal, 2-13, 9-2

TDO Signal, 2-13, 9-2, 9-4

Test Access Port, 9-1

TG Bit, 8-6, 8-8, 8-23–8-24, 8-27

TGE Bit, 8-8–8-11, 8-15, 8-24, 8-27

TGL Bit, 8-7, 8-24

Thermal Characteristics, 11-1

Three Point Three Volts, 10-11

Timeout, 8-2, 8-7–8-9, 8-12, 8-15

Timer

Bypass, 8-16

Clock Selection Logic, 8-3

Compare Function, 8-2, 8-6–8-9, 8-11–8-12, 8-14,

8-15, 8-25

Counter, 8-2

Counting Function, 8-13, 8-15

Gate Signal, 2-12, 8-6, 8-7–8-16, 8-21, 8-24–8-25

Input Signal, 2-12, 8-2, 8-5–8-17

Interrupt Operation, 8-4, 8-17, 8-19, 8-21,

8-23–8-24, 8-27

Output Signal, 2-12, 8-2, 8-5–8-17

Prescaler, 8-2–8-3, 8-21

Programming Model, 8-28

Uses, 8-2

Using to Compare Values, 8-6–8-8

TMS Signal, 2-13, 9-2

TO Bit, 8-8–8-9, 8-23–8-24, 8-27

Toggle Mode, 8-23

TP Bit, 5-61

TR Bit, 5-56, 5-58, 5-61

Trace

Exception, 5-57

Modes, 5-10

on Instruction Execution, 5-63

Tracing, 5-56–5-58

Control Bits Encoding, 5-53

Transfer Cases, 3-5

Mechanism, 3-5, 3-16–3-18

Transition to Background Mode, 5-65–5-68

Transmit

Data Signal, 2-11

Shift Register, 7-9, 7-11

Transmitter, 7-10–7-11

Baud Rates, 7-27

Buffer, 7-9–7-10, 7-25, 7-30–7-31

Disable Command, 7-29

Enable Command, 7-29

Holding Register, 7-9–7-10, 7-25, 7-33

Ready Signal, 2-11

Timing, 7-10

TRAP Instruction, 5-46

Two-Clock Bus Cycles, 10-3

TxCTS Bit, 7-39, 7-47

TxDx Signal, 7-3, 7-6, 7-10, 7-14, 7-29

TxEMP Bit, 7-10, 7-25, 7-28

TxRDY Bit, 7-10, 7-25, 7-28, 7-31

TxRDYA Bit, 7-34–7-35

TxRDYA Signal, 7-7, 7-36

TxRDYB Bit, 7-33, 7-35

TxRTS Bit, 7-38, 7-47

Types of DMA Interrupts, 6-20

— U —

Unimplemented Instructions, 5-12

Emulation, 5-74

Exception, 5-48, 5-50

UNLK Instruction, 5-36

Use of Chip Selects, 4-15, 10-3–10-4

User

Privilege Level, 5-7, 5-37–5-38, 5-48

Using

8-Bit Boot ROM, 10-5

TGATE as an Input Port, 8-16

Table Lookup and Interpolate Instructions, 5-7, 5-12,

5-20–5-35

TOUT as an Output Port, 8-16–8-17

— V —

V Bit, 4-14–4-15, 4-20, 4-31, 4-36

Variable Duty-Cycle Square-Wave Generator, 8-9–8-10

Variable-Width Single-Shot Pulse Generator, 8-10–8-12

VCCSYN, 2-13, 4-9–4-11, 10-2–10-3

Vector Base Register, 5-4, 5-10, 5-39–5-41, 5-43

Vector Numbers, 5-34–5-40

Virtual Memory, 5-2

Voltage-Controlled Oscillator, 4-9–4-12, 4-28–4-29,

10-1–10-2

— W —

W Bit, 4-10, 4-12–4-13, 4-28, 4-36

Wait States, 3-14, 3-16–3-20, 4-1, 4-14–4-15, 4-17,

4-32

Wakeup Mode, 7-15

Word Operands, 5-12

WP Bit, 4-14

Write

A/D Register Command, 5-77–5-79

Cycle Word, Flowchart, 3-18

Memory Location Command, 5-79–5-80

System Register Command, 5-78–5-79

Write-Pending Buffer, 5-91

— X —

X Bit, 4-9, 4-11–4-13, 4-28, 4-36

X1 Signal, 2-11, 7-5

X2 Signal, 2-11, 7-5

XFC Pin, 2-9, 4-12, 10-2–10-3

XTAL Pin, 2-9, 4-9–4-11, 10-1–10-2

XTAL_RDY Bit, 7-4, 7-26, 7-33–7-34, 7-46

Freescale Semiconductor, Inc.

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