AD1935 datasheet(24/30 Pages) AD

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AD1935/AD1936/AD1937/AD1938/AD1939

Preliminary Technical Data

Rev. Pr

I | Page 24 of 30

PLL AND CLOCK CONTROL REGISTERS

PLL and Clock control 0

Bit

Value

Function

Description

Normal operation

Power down

PLL power down

2:1

INPUT 256 (x 44.1 or 48kHz)

INPUT 384 (x 44.1 or 48kHz)

INPUT 512 (x 44.1 or 48kHz)

INPUT 768 (x 44.1 or 48kHz)

MCLK pin functionality (PLL active)

4:3

XTAL Oscillator Enabled

256xfs VCO Output

512xfs VCO Output

Off

MCLK_O pin

6:5

MCLK

DLRCLK

ALRCLK

Reserved

PLL input

Disable: ADC and DAC Idle

Enable: ADC and DAC Active

Internal MCLK Enable

Table 18

PLL and Clock control 1

Bit

Value

Function

Description

PLL Clock

MCLK

DAC Clock Source Select

PLL Clock

MCLK

ADC Clock Source Select

Enabled

Disabled

On-chip Voltage Reference

Not Locked

Locked

PLL Lock Indicator (Read Only)

7:4

0000

Reserved

Table 19

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