AD5666 datasheet(15/28 Pages) AD

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AD5666

Rev. A | Page 15 of 28

VLOGIC (V)

4.0

0.5

2.5

3.0

3.5

1.0

1.5

2.0

0123

456

VDD =5V

VDD =3V

TA = 25°C

Figure 24. Supply Current vs. Logic Input Voltage

TIME BASE = 4

μs/DIV

VDD =VREF =5V

TA =25°C

FULL-SCALE CODE CHANGE

0x0000 TO 0xFFFF

OUTPUT LOADED WITH 2kΩ

AND 200pF TO GND

VOUT = 909mV/DIV

Figure 25. Full-Scale Settling Time

CH1 2.0V

CH2 500mV

M100

μs 125MS/s

A CH1

1.28V

8.0ns/pt

VDD =VREF =5V

TA =25°C

VOUT

VDD

MAX(C2)*

420.0mV

Figure 26. Power-On Reset to 0 V

CH1 2.0V

CH2 1.0V

M100

μs 125MS/s

A CH1

1.28V

8.0ns/pt

VDD =VREF =5V

TA =25°C

VOUT

VDD

Figure 27. Power-On Reset to Midscale

VDD = 5V

SYNC

SLCK

VOUT

CH1 5.0V

CH3 5.0V

CH2 500mV

M400ns

A CH1

1.4V

Figure 28. Exiting Power-Down to Midscale

SAMPLE

2.505

2.485

512

128

192

256

320

384

448

VDD =5V

VREFOUT =2.5V

TA = 25°C

4ns/SAMPLE NUMBER

GLITCH IMPULSE = 3.55nV-s

1 LSB CHANGE AROUND

MIDSCALE (0x8000 TO 0x7FFF)

2.486

2.487

2.488

2.489

2.490

2.491

2.492

2.493

2.494

2.495

2.496

2.497

2.498

2.499

2.500

2.501

2.502

2.503

2.504

Figure 29. Digital-to-Analog Glitch Impulse

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