AD5666 datasheet(23/28 Pages) AD

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AD5666

Rev. A | Page 23 of 28

DAISY-CHAINING

For systems that contain several DACs, or where the user

wishes to read back the DAC contents for diagnostic purposes,

the SDO pin can be used to daisy-chain several devices together

and provide serial readback.

The daisy-chain mode is enabled through a software executable

DCEN command. Command 1000 is reserved for this DCEN

function (see Table 7). The daisy-chain mode is enabled by

setting a bit (DB1) in the DCEN register. The default setting is

standalone mode, where Bit DCEN = 0. Table 9 shows how the

state of the bits corresponds to the mode of operation of the

device.

The SCLK is continuously applied to the input shift register

when SYNC is low. If more than 32 clock pulses are applied, the

data ripples out of the shift register and appears on the SDO

line. This data is clocked out on the rising edge of SCLK and is

valid on the falling edge. By connecting this line to the DIN

input on the next DAC in the chain, a multi-DAC interface is

constructed. Each DAC in the system requires 32 clock pulses;

therefore, the total number of clock cycles must equal 32N,

where N is the total number of devices in the chain.

When the serial transfer to all devices is complete, SYNC is

taken high. This prevents any further data from being clocked

into the input shift register.

If SYNC is taken high before 32 clocks are clocked into the part,

it is considered an invalid frame and the data is discarded.

The serial clock can be continuous or a gated clock. A con-

tinuous SCLK source can be used only if the SYNC can be held

low for the correct number of clock cycles. In gated clock mode,

a burst clock containing the exact number of clock cycles must

be used, and SYNC must be taken high after the final clock to

latch the data.

INTERNAL REFERENCE REGISTER

The on-board reference is off at power-up by default. This

allows the use of an external reference if the application requires

it. The on-board reference can be turned on/off by a user-

programmable REF register by setting Bit DB0 high or low (see

Table 9). Command 1000 is reserved for this internal REF set-

up command (see Table 7). Table 11 shows how the state of the

bits in the input shift register corresponds to the mode of

operation of the device.

POWER-ON RESET

The AD5666 contains a power-on reset circuit that controls the

output voltage during power-up. By connecting the POR pin

low, the AD5666 output powers up to 0 V; by connecting the

POR pin high, the AD5666 output powers up to midscale. The

output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the DAC

while it is in the process of powering up. There is also a software

executable reset function that resets the DAC to the power-on

reset code. Command 0111 is reserved for this reset function

(see Table 7). Any events on LDAC or CLR during power-on

reset are ignored.

POWER-DOWN MODES

The AD5666 contains four separate modes of operation.

Command 0100 is reserved for the power-down function (see

Table 7). These modes are software-programmable by setting

two bits, Bit DB19 and Bit DB18, in the control register. Table 11

shows how the state of the bits corresponds to the mode of

operation of the device. Any or all DACs (DAC D to DAC A)

can be powered down to the selected mode by setting the cor-

responding four bits (DB7, DB6, DB1, DB0) to 1. See Table 12

for the contents of the input shift register during power-down/

power-up operation. When using the internal reference, only

all channel power-down to the selected modes is supported.

When both bits are set to 0, the part works normally with its

normal power consumption of 700 μA at 5 V. However, for the

three power-down modes, the supply current falls to 400 nA at

5 V (200 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 44.

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. The internal reference is powered down only

when all channels are powered down. However, the contents of

the DAC register are unaffected when in power-down. The time

to exit power-down is typically 4 μs for VDD = 5 V and for

VDD = 3 V (see Figure 28).

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC Low) or to the value in the

DAC register before powering down (LDAC high).

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