AD5666 datasheet(22/28 Pages) AD

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AD5666

Rev. A | Page 22 of 28

INPUT SHIFT REGISTER

The input shift register is 32 bits wide (see Figure 42). The first

four bits are don’t cares. The next four bits are the command

bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address

bits, A3 to A0 (see Table 9) and finally the 16-bit data-word.

The data-word comprises the 16-bit input code followed by four

don’t care bits for the AD5666 (see Figure 42). These data bits

are transferred to the DAC register on the 32nd falling edge of

SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 32 falling edges of SCLK, and the DAC is updated on the

32nd falling edge. However, if SYNC is brought high before the

32nd falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 43).

ADDRESS BITS

COMMAND BITS

D15 D14 D13 D12 D11 D10

XXX

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 42. AD5666 Input Register Content

SCLK

DIN

DB31

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 32ND FALLING EDGE

DB31

DB0

SYNC

Figure 43. SYNC Interrupt Facility

AD5666 Datasheet(PDF) 22 Page - Analog Devices