ADV7180 datasheet(72/112 Pages) AD

72 / 112 page

ADV7180

Rev. A | Page 72 of 112

PIXEL PORT CONFIGURATION

The ADV7180 has a very flexible pixel port that can be

configured in a variety of formats to accommodate downstream

ICs. Table 96, Table 97, and Table 98 summarize the various

functions that the ADV7180 pins can have in different modes of

operation.

The ordering of components, for example, Cr vs. Cb for

Channels A, B, and C can be changed. Refer to the SWPC, Swap

Pixel Cr/Cb, Address 0x27 [7] section. Table 96 indicates the

default positions for the Cr/Cb components.

OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2]

The modes in which the ADV7180 pixel port can be configured

are under the control of OF_SEL[3:0]. See Table 98 for details.

The default LLC frequency output on the LLC1 pin is approxi-

mately 27 MHz. For modes that operate with a nominal data rate

of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin

stays at the higher rate of 27 MHz. For information on outputting

the nominal 13.5 MHz clock on the LLC1 pin, see the section

LLC_PAD_SEL[2:0], LLC1 Output Selection,

Address 0x8F [6:4].

SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]

This bit allows Cr and Cb samples to be swapped.

When SWPC is 0 (default), no swapping is allowed.

When SWPC is 1, the Cr and Cb values can be swapped.

LLC_PAD_SEL[2:0], LLC1 Output Selection,

Address 0x8F [6:4]

The following I2C write allows the user to select between LLC1

(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).

The LLC2 signal is useful for LLC2-compatible wide bus

(16-bit) output modes. See the OF_SEL[3:0], Output Format

Selection, Address 0x03 [5:2] section for additional information.

The LLC2 signal and data on the data bus are synchronized.

By default, the rising edge of LLC1/LLC2 is aligned with the

Y data; the falling edge occurs when the data bus holds C data.

The polarity of the clock, and therefore the Y/C assignments to

the clock edges, can be altered by using the polarity LLC pin.

When LLC_PAD_SEL is 000, the output is nominally 27 MHz

LLC on the LLC1 pin (default).

When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz

LLC on the LLC2 pin.

Table 96. ADV7180 LQFP-64 P15 to P0 Output/Input Pin Mapping

Data Port Pins P[15:0]

Format and Mode

Video Out, 8-Bit, 4:2:2

YCrCb[7:0]OUT

Video Out, 16-Bit, 4:2:2

Y[7:0]OUT

CrCb[7:0]OUT

Table 97. ADV7180 LFCSP-40 P7 to P0 Output/Input Pin Mapping

Data Port Pins P[7:0]

Format and Mode

Video Out, 8-Bit, 4:2:2

YCrCb[7:0]OUT

Table 98. ADV7180 Standard Definition Pixel Port Modes

ADV7180 LQFP-64 P[15: 0]

ADV7180 LFCSP-40

OF_SEL[3:0]

Format

P[15:8]

P[7: 0]

0000 to 0001

Reserved

Reserved, do not use

0010

16-bit @ LLC2 4:2:2

Y[7:0]

CrCb[7:0]

Not valid

0011 (Default)

8-bit @ LLC1 4:2:2 (default)

YCrCb[7:0]

Three-state

YCrCb[7:0]

0100 to 1111

Reserved

Reserved, do not use

ADV7180 Datasheet(PDF) 72 Page - Analog Devices

ADV7180 Datasheet(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL