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ADV7180 Datasheet(PDF) 13 Page - Analog Devices |
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ADV7180 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 112 page  ADV7180 Rev. A | Page 13 of 113 64-LEAD LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47 AIN4 46 AIN3 45 NC 42 NC 43 AGND 44 NC 48 AIN5 41 NC 40 AVDD 39 VREFN 37 AGND 36 AIN2 35 AIN1 34 TEST_0 33 NC 38 VREFP 2 HS 3 DGND 4 DVDDIO 7 P9 6 P10 5 P11 1 INTRQ 8 P8 9 SFL 10 DGND 12 GPO1 13 GPO0 14 P7 15 P6 16 P5 11 DVDDIO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN 1 ADV7180 LQFP TOP VIEW (Not to Scale) NC = NO CONNECT Figure 8. 64-Lead LQFP Pin Configuration Table 9. Pin Function Description for the ADV7180 LQFP-64 Pin No. Mnemonic Type Function 3, 10, 24, 57 DGND G Digital Ground. 32, 37, 43 AGND G Analog Ground. 4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V). 23, 58 DVDD P Digital Supply Voltage (1.8 V). 40 AVDD P Analog Supply Voltage (1.8 V). 31 PVDD P PLL Supply Voltage (1.8 V). 38 VREFP O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry. 39 VREFN O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry. 35, 36, 46 to 49 AIN1 to AIN6 I Analog Video Input Channels. 27, 28, 33, 41, 42, 44, 45, 50 NC No Connect Pins. These pins are not connected internally. 5 to 8, 14 to 19, 25, 26, 59 to 62 P11 to P8, P7 to P2, P1, P0, P15 to P12 O Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes. 2 HS O Horizontal Synchronization Output Signal. 64 VS O Vertical Synchronization Output Signal. 63 FIELD O Field Synchronization Output Signal. 1 INTRQ O Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video (see Table 104). 53 SDATA I/O I2C Port Serial Data Input/Output Pin. 54 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. 52 ALSB I This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42. 29 PWRDWN I A logic low on this pin places the ADV7180 in power-down mode. 30 ELPF I The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 54. 51 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry. |
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