AD7324 datasheet(17/36 Pages) AD

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AD7324

Rev. 0 | Page 17 of 36

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

AGND

SW2

SW1

VIN0

The ideal transfer characteristic for the AD7324 when twos

complement coding is selected is shown in Figure 27. The ideal

transfer characteristic for the AD7324 when straight binary

coding is selected is shown in Figure 28.

011...111

011...110

000...001

000...000

111...111

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB

UNIPOLAR RANGE

AGND – 1LSB

ANALOG INPUT

100...010

100...001

100...000

Figure 24. ADC Conversion Phase (Single-Ended)

Figure 25 shows the differential configuration during the

acquisition phase. For the conversion phase, SW3 opens and

SW1 and SW2 move to Position B (Figure 26). The output

impedances of the source driving the VIN+ and VIN− pins must

be matched; otherwise, the two inputs will have different

settling times, resulting in errors.

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

COMPARATOR

SW3

SW1

VIN+

SW2

VIN–

VREF

Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)

111...111

111...110

111...000

011...111

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB

UNIPOLAR RANGE

ANALOG INPUT

000...010

000...001

000...000

Figure 25. ADC Differential Configuration During Acquisition Phase

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

COMPARATOR

SW3

SW1

VIN+

SW2

VIN–

VREF

Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)

ANALOG INPUT STRUCTURE

The analog inputs of the AD7324 can be configured as single-

ended, true differential, or pseudo differential via the control

bipolar input signals. On power-up, the analog inputs operate as

four single-ended analog input channels. If true differential or

pseudo differential is required, a write to the control register is

necessary after power-up to change this configuration.

Figure 26. ADC Differential Configuration During Conversion Phase

Output Coding

The AD7324 default output coding is set to twos complement.

The output coding is controlled by the coding bit in the control

the coding bit in the control register must be set. When

operating in sequence mode, the output coding for each

channel in the sequence is the value written to the coding bit

during the last write to the control register.

Figure 29 shows the equivalent analog input circuit of the

AD7324 in single-ended mode. Figure 30 shows the equivalent

analog input structure in differential mode. The two diodes

provide ESD protection for the analog inputs.

VDD

VIN0

VSS

Transfer Functions

The designed code transitions occur at successive integer

LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is

dependent on the analog input range selected.

Table 7. LSB Sizes for Each Analog Input Range

Figure 29. Equivalent Analog Input Circuit (Single-Ended)

Input Range

Full-Scale Range/8192 Codes

LSB Size

±10 V

20 V

2.441 mV

±5 V

10 V

1.22 mV

±2.5 V

5 V

0.61 mV

0 V to +10 V

10 V

1.22 mV

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