AD7324 datasheet(29/36 Pages) AD

29 / 36 page

AD7324

Rev. 0 | Page 29 of 36

MODES OF OPERATION

The AD7324 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements. The mode of

operation of the AD7324 is controlled by the power manage-

ment bits, Bit PM1 and Bit PM0, in the control register as shown

The AD7324 remains fully powered up at the end of the

conversion if both PM1 and PM0 contain 0 in the control

To complete the conversion and access the conversion result

16 serial clock cycles are required. At the end of the conversion,

CS can idle either high or low until the next conversion.

Table 11. The default mode is normal mode, where all internal

circuitry is fully powered up.

Once the data transfer is complete, another conversion can be

initiated after the quiet time, tQUIET, has elapsed.

NORMAL MODE

(PM1 = PM0 = 0)

FULL SHUTDOWN MODE

(PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate

performance, with the AD7324 being fully powered up at all

times.

In this mode, all internal circuitry on the AD7324 is powered

down. The part retains information in the registers during full

shutdown. The AD7324 remains in full shutdown mode until

the power management bits, Bit PM1 and Bit PM0, in the

control register are changed.

Figure 46 shows the general operation of the AD7324

in normal mode.

The conversion is initiated on the falling edge of CS, and the

track-and-hold enters hold mode as described in the Serial

Interface section. Data on the DIN line during the 16 SCLK

transfer is loaded into one of the on-chip registers if the write

bit is set. The register is selected by programming the register

select bits (see

A write to the control register with PM1 = 1 and PM0 = 1 places

the part into full shutdown mode. The AD7324 enters full shut-

down mode on the 15th SCLK rising edge rising edge once the

control register is updated.

Figure 46).

LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +

CONVERSION RESULT

DATA INTO CONTROL/SEQUENCE/RANGE REGISTER

SCLK

DOUT

DIN

If a write to the control register occurs while the part is in full

shutdown mode with the power management bits, Bit PM1 and

Bit PM0, set to 0 (normal mode), the part begins to power up

on the 15th SCLK rising edge once the control register is

updated. Figure 47 shows how the AD7324 is configured to exit

full shutdown mode. To ensure the AD7324 is fully powered up,

tPOWER-UP for full shutdown mode should elapse before the next

CS falling edge

Figure 46. Normal Mode

116

SCLK

SDATA

DIN

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA INTO CONTROL REGISTER

tPOWER-UP

THE PARTIS FULLY POWERED UP

ONCE

tPOWER-UP HAS ELAPSED

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 0, PM0 = 0

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0

IN CONTROL REGISTER

PART IS IN FULL

SHUTDOWN

PART BEGINS TO POWER UP ON THE 15TH

SCLK RISING EDGE AS PM1 = PM0 = 0

Figure 47. Exiting Full Shutdown Mode

AD7324 Datasheet(PDF) 29 Page - Analog Devices

AD7324 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL