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AD7324

Rev. 0 | Page 31 of 36

1000

THROUGHPUT RATE (kHz)

100

200

300

400

500

600

700

800

900

20MHz SCLK

VARIABLE SCLK

VCC =5V

VDD/VSS = ±12V

TA = 25°C

INTERNAL REFERENCE

POWER VS. THROUGHPUT RATE

The power consumption of the AD7324 varies with throughput

rate. The static power consumed by the AD7324 is very low, and

a significant power savings can be achieved as the throughput

rate is reduced. Figure 49 and Figure 50 shows the power vs.

throughput rate for the AD7324 at a VCC of 3 V and 5 V,

respectively. Both plots clearly show that the average power

consumed by the AD7324 is greatly reduced as the sample

frequency is reduced. This is true whether a fixed SCLK value is

used or if it is scaled with the sampling frequency. Figure 49 and

Figure 50 show the power consumption when operating in

normal mode for a fixed 20 MHz SCLK and a variable SCLK

that scales with the sampling frequency.

1100

THROUGHPUT RATE (kSPS)

100 200 300 400 500 600 700 800 900 1000

VARIABLE SCLK

20MHz SCLK

VCC =3V

VDD/VSS = ±12V

TA = 25°C

INTERNAL REFERENCE

Figure 50. Power vs. Throughput Rate with 5 V VCC

Figure 49. Power vs. Throughput Rate with 3 V VCC

AD7324 Datasheet(PDF) 31 Page - Analog Devices

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