AD7324 datasheet(32/36 Pages) AD

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AD7324

Rev. 0 | Page 32 of 36

SERIAL INTERFACE

Figure 51 shows the timing diagram for the serial interface of

the AD7324. The serial clock applied to the SCLK pin provides

the conversion clock and controls the transfer of information to

and from the AD7324 during a conversion.

Data is clocked into the AD7324 on the SCLK falling edge. The

3 MSBs on the DIN line are decoded to select which register is

being addressed. The control register is a 12-bit register. If the

control register is addressed by the 3 MSBs, the data on the DIN

line is loaded into the control on the 15th SCLK rising edge. If the

sequence register or the range register is addressed, the data on

the DIN line is loaded into the addressed register on the 11th SCLK

falling edge.

The

signal initiates the data transfer and the conversion

process. The falling edge of CS puts the track-and-hold into

hold mode and takes the bus out of three-state. Then the analog

input signal is sampled. Once the conversion is initiated,

it requires 16 SCLK cycles to complete.

Conversion data is clocked out of the AD7324 on each SCLK

falling edge. Data on the DOUT line consists of a leading ZERO

bit, two channel identifier bits, a sign bit, and a 12-bit conversion

result. The channel identifier bits are used to indicate which

channel corresponds to the conversion result. The leading ZERO

bit is clocked out on the

The track-and-hold goes back into track mode on the 14th SCLK

rising edge. On the 16th SCLK falling edge, the DOUT line returns

to three-state. If the rising edge of CS occurs before 16 SCLK cycles

have elapsed, the conversion is terminated, and the DOUT line

returns to three-state. Depending on where the

CS falling edge, and the first channel

identifier bit is clocked out on the first SCLK falling edge.

CS signal is brought

high, the addressed register may be updated.

ADD1

WRITE

REG

SEL1

REG

SEL2

LSB

MSB

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

t10

tQUIET

tCONVERT

SCLK

DOUT

THREE-

STATE

THREE-STATE

DIN

ZERO

2 IDENTIFICATION BITS

DON’T

CARE

Figure 51. Serial Interface Timing Diagram (Control Register Write)

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