AD7329 datasheet(35/40 Pages) AD

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AD7329

Rev. 0 | Page 35 of 40

SERIAL INTERFACE

Figure 57 shows the timing diagram for the serial interface of

the AD7329. The serial clock applied to the SCLK pin provides

the conversion clock and controls the transfer of information to

and from the AD7329 during a conversion.

The CS signal initiates the data transfer and the conversion

process. The falling edge of CS puts the track-and-hold section

into hold mode and takes the bus out of three-state. The analog

input signal is then sampled. Once the conversion is initiated,

it requires 16 SCLK cycles to complete.

The track-and-hold section goes back into track mode on the

14th SCLK rising edge. On the 16th SCLK falling edge, the

DOUT line returns to three-state. If the rising edge of CS occurs

before 16 SCLK cycles have elapsed, the conversion is

terminated and the DOUT line returns to three-state. Depending

on where the CS signal is brought high, the addressed register

may be updated.

Data is clocked into the AD7329 on the SCLK falling edge. The

three MSBs on the DIN line are decoded to select which register

is addressed. The control register is a 12-bit register. If the

control register is addressed by the three MSBs, the data on the

DIN line is loaded into the control on the 15th SCLK rising edge.

If the sequence register or either of the range registers is

addressed, the data on the DIN line is loaded into the addressed

Conversion data is clocked out of the AD7329 on each SCLK

falling edge. Data on the DOUT line consists of three channel

identifier bits, a sign bit, and a 12-bit conversion result. The

channel identifier bits are used to indicate which channel

corresponds to the conversion result.

If the Weak/Three-State bit is set in the control register, rather

than returning to true three-state upon the 16th SCLK falling

edge, the DOUT line is pulled weakly to the logic level

corresponding to ADD3 of the next serial transfer. This is done

to ensure that the MSB of the next serial transfer is set up in

time for the first SCLK falling edge after the CS falling edge. If

the Weak/Three-State bit is set to 0 and the DOUT line returns

to true three-state between conversions, then depending on the

particular processor interfacing to the AD7329, the ADD3 bit

may be valid in time for the processor to clock it in successfully.

If the Weak/Three-State bit is set to 1, then although the DOUT

line has been driven to ADD3 since the previous conversion, it

is nevertheless so weakly driven that another device could take

control of the bus. This will not lead to a bus contention issue

because, for example, a 10 kΩ pull-up or pull-down resister is

sufficient to overdrive the logic level of ADD3. When the

Weak/Three-State bit is set to 1, the ADD3 is typically valid 9 ns

after the CS falling edge, compared with 14 ns when the DOUT

line returns to three-state at the end of the conversion.

ADD1

WRITE

REG

SEL1

REG

SEL2

LSB

MSB

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

t10

tQUIET

tCONVERT

SCLK

DOUT

THREE-

STATE

THREE-STATE

DIN

ADD2

3 IDENTIFICATION BITS

Figure 57. Serial Interface Timing Diagram (Control Register Write)

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