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AD7329 Datasheet(PDF) 34 Page - Analog Devices |
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AD7329 Datasheet(HTML) 34 Page - Analog Devices |
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34 / 40 page ![]() AD7329 Rev. 0 | Page 34 of 40 POWER VS. THROUGHPUT RATE The power consumption of the AD7329 varies with throughput rate. The static power consumed by the AD7329 is very low, and significant power savings can be achieved as the throughput rate is reduced. Figure 55 and Figure 56 shows the power vs. throughput rate for the AD7329 at a VCC of 3 V and 5 V, respectively. Both plots clearly show that the average power consumed by the AD7329 is greatly reduced as the sample frequency is reduced. This is true whether a fixed SCLK value is used or if it is scaled with the sampling frequency. Figure 55 and Figure 56 show the power consumption when operating in normal mode for a fixed 20 MHz SCLK and a variable SCLK that scales with the sampling frequency. 12 0 0 1100 THROUGHPUT RATE (kSPS) 10 8 6 4 2 100 200 300 400 500 600 700 800 900 1000 VARIABLE SCLK 20MHz SCLK VCC = 3V VDD = 12V, VSS = –12V TA = 25°C INTERNAL REFERENCE Figure 55. Power vs. Throughput Rate with 3 V VCC 20 0 0 1000 THROUGHPUT RATE (kHz) 18 16 14 12 10 8 6 4 2 100 200 300 400 500 600 700 800 900 20MHz SCLK VARIABLE SCLK VCC = 5V VDD = 12V, VSS = –12V TA = 25°C INTERNAL REFERENCE Figure 56. Power vs. Throughput Rate with 5 V VCC |
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