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LTM4709

Rev. 0

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through the LTM4709. While the output capacitor is par-

tially intended to absorb these spikes, its equivalent series

inductance (ESL) will limit its ability at these frequencies.

A ferrite bead or even the inductance associated with a

short (e.g., 0.5-inch) PCB trace between the switcher’s

output and the LTM4709’s input can serve as an LC-filter

to suppress these very high-frequency spikes.

Fast Start-Up

For ultralow noise applications that require low 1/f noise

(i.e., at frequencies below 100Hz), a larger value VREF

pin capacitor is required, up to 22μF. While this would

normally significantly increase the regulator’s start-up

time, the LTM4709 incorporates fast start-up circuitry

that increases VREF pin current to 2mA during start-up.

For a 22μF capacitor, this will reduce the startup time from

100ms to 5ms.

The 2mA current source remains engaged until VREF is

100% of its final value on the rising edge, and it will restart

when VOUT is below 94% of output setting on the falling

edge, unless the regulator is in current limit, thermal shut-

down, or UVLO situation.

Thermal Considerations and Output Current Derating

For application in high ambient temperature, care should

be taken in the PCB layout to ensure good heat transfer

from LTM4709 to the PCB. The VIN and VOUT should be

connected to large copper layers below with thermal vias.

The die temperature can be estimated by multiplying the

LTM4709 power dissipation by the thermal resistance

from the junction to the ambient.

The thermal picture when the LTM4709 is mounted on the

EVAL-LTM4709-BZ evaluation board and is operating at

1.3VIN, 1VOUT, and 9A load current with three channels

in parallel is shown in Figure 5. The highest temperature

of the module top case is 66°C and the currents of the

three channels are well balanced.

The internal overtemperature protection monitors the

junction temperature of the LTM4709. If the junction

temperature reaches 168°C, the LTM4709 output is shut

down until the temperature drops by 7°C.

Figure 5. Thermal Image, Full Load with Three Channels in

Parallel (1.3VIN, 1VOUT, 9A) without Fan, TA = 25°C

The thermal resistances reported in the Pin Configuration

section are consistent with those parameters defined by

JESD51-12 and are intended for use with finite element

analysis (FEA) software modeling tools that leverage the

outcome of thermal modeling, simulation, and correlation

to hardware evaluation performed on a μModule pack-

age mounted to a hardware test board. The motivation

for providing these thermal coefficients can be found in

JESD51-12 (Guidelines for Reporting and Using Electronic

Package Thermal Information).

Many designers may opt to use laboratory equipment and

a test vehicle such as the demo board to anticipate the

μModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without

FEA software, the thermal resistances reported in the

Pin Configuration section are, in-and-of themselves, not

relevant to providing guidance of thermal performance;

instead, the derating curves (Figure 7 to Figure 13) can

be used in a manner that yields insight and guidance per-

taining to one’s application usage and can be adapted to

correlate thermal performance to one’s own application.

The Pin Configuration section typically gives three thermal

coefficients explicitly defined in JESD51-12; these coeffi-

cients are quoted or paraphrased below.

1. θJA, the thermal resistance from junction to ambi-

ent, is the natural convection junction-to-ambient air

thermal resistance measured in one cubic foot sealed

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