LTM8063 datasheet(20/26 Pages) AD

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LTM4709

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

• Flood all unused areas on all layers with copper.

Flooding with copper will help release thermal stress.

Connect the copper areas to GND.

• Use solder mask defined round pads.

Figure 14 givesagoodexampleoftherecommended layout.

For a detailed recommended layout to optimize the low

noise and high PSRR performance, refer to the layout of

demo board DC3211A.

4709 F14

VIN2

VIN1

VIN3

COUT2

COUT1

COUT3

CIN2

CIN1

CIN3

VOUT2

VOUT1

VOUT3

GND

Figure 14. Recommended PCB Layout

Table 3. Output Voltage Response vs Component Matrix

COUT

VALUE

PART NUMBER

Murata

10μF, 6.3V, 1206, X7R

GRM31CR70J106K

Murata

22μF, 25V, 1206, X5R

GRM31CR61E226KE15L

VIN

(V)

VOUT

(V)

COUT

CERAMIC

(μF)

LOAD STEP

(A)

LOAD STEP

SLEW RATE

(A/μs)

P-P

DERIVATION (mV)

RECOVERY

TIME

(µs)

1.3

0.3 to 3

1.3

0.3 to 3

Safety Considerations

The LTM4709 μModule ICs do not provide galvanic

isolation from VIN to VOUT. There is no internal fuse. If

required, a slow blow fuse with a rating twice the maxi-

mum input current must be provided to protect each unit

from catastrophic failure. The device does support ther-

mal shutdown and short-circuit protection.

PCB Layout Checklist/Example

The high integration of LTM4709 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high-frequency ceramic input and output capac-

itors next to the VIN, GND and VOUT pins to minimize

high-frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• Use planes for VIN and VOUT to maintain good voltage

filtering and to keep power losses low.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between the top layer and other power layers.

• Do not put via directly on the pad unless they are

capped or plated over.

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