AD8107 datasheet(16/28 Pages) AD

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AD8106/AD8107

Rev. 0 | Page 16 of 28

THEORY OF OPERATION

The AD8106 (G = 1) and AD8107 (G = 2) share a common core

architecture consisting of an array of 80 transconductance (gm)

input stages that are organized as five 16:1 multiplexers with a

common, 16-line analog input bus. Each multiplexer is

essentially a folded-cascode high speed voltage, feedback

amplifier with 16 input stages. The input stages are NPN

differential pairs whose differential current outputs are

combined at the output stage, which contains the high

impedance node, compensation, and a complementary emitter

follower output buffer. In the AD8106, the output of each

multiplexer is fed directly back to the inverting inputs of its

16 gm stages. In the AD8107, the feedback network is a voltage

divider consisting of two equal-value resistors.

This switched-gm architecture results in a low power crosspoint

switch that is able to directly drive a back-terminated video load

(150 Ω) with low distortion (differential gain and differential

phase errors are better than 0.02% and 0.02°, respectively). This

design also achieves high input resistance and low input

capacitance without the signal degradation and power

dissipation of additional input buffers. However, the small input

bias current at any input increases almost linearly with the

number of outputs programmed to that input.

The output disable feature of these crosspoints allows larger

switch matrices to be built simply by busing together the

outputs of multiple 16 × 5 ICs. However, while the disabled

output impedance of the AD8106 is very high (10 MΩ), the

AD8107 output impedance is limited by the resistive feedback

network, which has a nominal total resistance of 1 kΩ and

appears in parallel with the disabled output. If the outputs of

multiple AD8107s are connected through separate back

termination resistors, the loading lowers the effective back

termination impedance of the overall matrix because of these

finite output impedances. This problem is eliminated if the

outputs of multiple AD8107s are connected directly and share a

single back-termination resistor for each output of the overall

matrix. This configuration increases the capacitive loading of

the disabled AD8107 on the output of the enabled AD8107.

POWER-ON RESET

When powering up the AD8106/AD8107, it is usually necessary

to have the outputs be in the disabled state. The RESET pin,

when taken low, causes all outputs to be in the disabled state.

The RESET pin has a 20 kΩ pull-up resistor to DVDD that can

be used to create a simple power-up reset circuit. A capacitor

from RESET to ground holds RESET low for some time while

the rest of the device stabilizes. The low condition causes all the

outputs to disable. The capacitor then charges through the pull-

up resistor to the high state, allowing full programming

capability of the device.

INITIALIZATION

The AD8106/AD8107 should be initialized after power up to

control the supply and bias currents, and to make sure that no

unexpected program states are encountered. Initialization is

performed by writing a data word of 00000 into all address

locations 00 to 07 (000 to 111 binary).

GAIN SELECTION

The 16 × 5 crosspoints come in two versions depending on the

desired gain of the analog circuit paths. The AD8106 device is

unity gain and can be used for analog logic switching and other

applications where unity gain is desired. The AD8106 can also

be used for the input and interior sections of larger crosspoint

arrays where termination of output signals is not usually used.

The AD8106 outputs have very high impedance when their

outputs are disabled.

For devices that drive a terminated cable with its outputs, the

AD8107 can be used. This device has a built-in gain of two that

eliminates the need for a gain-of-two buffer to drive a video

line. Because of the presence of the feedback network in these

devices, the disabled output impedance is about 1 kΩ.

CREATING LARGER CROSSPOINT ARRAYS

The AD8106/AD8107 are high density building blocks that

create crosspoint arrays for dimensions larger than 16 × 5.

Various features such as output disable, chip enable, and gain-

of-one and gain-of-two options are useful for creating larger

arrays. For very large arrays, they can be used with the

AD8114/AD8115, 16 × 16 video crosspoint devices, or the

AD8110/AD8111, 16 x 8 video crosspoint devices. When required

for customizing a crosspoint array size, the parts can also be

used with the AD8108 and AD8109, a pair (unity gain and

gain-of-two) of 8 × 8 video crosspoint switches.

The first consideration in constructing a larger crosspoint is to

determine the minimum number of required devices. The 16 × 5

architecture of the AD8106/AD8107 contains 80 points. For a

nonblocking crosspoint, the number of points required is the

product of the number of inputs multiplied by the number of

outputs. Nonblocking requires that the programming of a given

input to one or more outputs does not restrict the availability of

that input to be a source for any other output.

Some nonblocking crosspoint architectures require more than this

minimum as calculated above. In addition, there are blocking

architectures that can be constructed with fewer devices than this

minimum. These systems have connectivity available on a statistical

basis that is determined when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to

connect inputs in parallel in a horizontal direction and to wire-OR

the outputs together in a vertical direction.

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