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AD9481 Datasheet(PDF) 7 Page - Analog Devices |
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AD9481 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 28 page  AD9481 Rev. 0 | Page 7 of 28 TIMING DIAGRAM INTERLEAVED DATA OUT VIN CLK+ CLK– D7A TO D0A PORT A STATIC INVALID N N–1 N+1 8 CYCLES N+7 N+8 N+9 N+10 N D7B TO D0B PORT B STATIC INVALID INVALID N+1 tV tPD tEH DS+ DS– tHDS tSDS tA tEL 1/fS DCO+ DCO– STATIC tCPD tSKA tSKB Figure 2. Timing Diagram |
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