Philips Semiconductors

Product data

89C51/89C52/89C54/89C58

80C51 8-bit microcontroller family

4K/8K/16K/32K Flash

2002 Jan 15

25

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

External interrupt 0

1

IE0

03H

Timer 0

2

TF0

Y

0BH

External interrupt 1

3

IE1

N (L)

Y (T)

13H

Timer 1

4

TF1

Y

1BH

UART

5

RI, TI

N

23H

Timer 2

6

TF2, EXF2

N

2BH

NOTES:

1. L = Level activated

2. T = Transition activated

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output, unless the CPU needs to perform an off-chip memory access.

AUXR

Reset Value = xxxx xxx0B

—

——

——

—

—

AO

Symbol

Function

AO

Disable/Enable ALE

AO

Operating Mode

0

1

ALE is active only during off-chip memory accesses.

—

SU01560

7654

321

0

Address = 8EH

Not Bit Addressable

1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that

case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Figure 15. AUXR: Auxiliary Register