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89C52 Datasheet(PDF) 29 Page - NXP Semiconductors |
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89C52 Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 39 page  Philips Semiconductors Product data 89C51/89C52/89C54/89C58 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 2002 Jan 15 29 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 18 Oscillator frequency Speed versions 3.5 33 3.5 33 MHz tLHLL 18 ALE pulse width 2tCLCL–40 21 ns tAVLL 18 Address valid to ALE low tCLCL–25 5 ns tLLAX 18 Address hold after ALE low tCLCL–25 5 ns tLLIV 18 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 18 ALE low to PSEN low tCLCL–25 5 ns tPLPH 18 PSEN pulse width 3tCLCL–45 45 ns tPLIV 18 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 18 Input instruction hold after PSEN 0 0 ns tPXIZ 18 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 18 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 18 PSEN low to address float 10 10 ns Data Memory tRLRH 19, 20 RD pulse width 6tCLCL–100 82 ns tWLWH 19, 20 WR pulse width 6tCLCL–100 82 ns tRLDV 19, 20 RD low to valid data in 5tCLCL–90 60 ns tRHDX 19, 20 Data hold after RD 0 0 ns tRHDZ 19, 20 Data float after RD 2tCLCL–28 32 ns tLLDV 19, 20 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 19, 20 Address to valid data in 9tCLCL–165 105 ns tLLWL 19, 20 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 19, 20 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 19, 20 Data valid to WR transition tCLCL–30 0 ns tWHQX 19, 20 Data hold after WR tCLCL–25 5 ns tQVWH 20 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 19, 20 RD low to address float 0 0 ns tWHLH 19, 20 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 22 High time 17 tCLCL–tCLCX ns tCLCX 22 Low time 17 tCLCL–tCHCX ns tCLCH 22 Rise time 5 ns tCHCL 22 Fall time 5 ns Shift Register tXLXL 21 Serial port clock cycle time 12tCLCL 360 ns tQVXH 21 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 21 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 21 Input data hold after clock rising edge 0 0 ns tXHDV 21 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are guaranteed to operate down to 0 Hz. |
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