CS3318 datasheet(27/44 Pages) CIRRUS

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DS693F1

CS3318

5.9

I²C/SPI Serial Control Formats

The control port is used to access the internal registers of the CS3318. The control port has 2 modes: SPI

and I²C, with the CS3318 acting as a slave device. SPI Mode is selected if there is a high-to-low transition

on the CS pin after the RESET pin has been brought high. I²C Mode is selected by connecting the CS pin

to VD or DGND.

5.9.1

I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the CS3318 by the clock,

SCL. The AD0 pin sets the least significant bit of the default chip address and must be connected to VD

or DGND. The AD0 pin is read upon the release of the RESET signal (a low-to-high transition), and its

value (‘0’ when connected to DGND, ‘1’ when connected to VD) is reflected in the LSB of the chip address

in the Individual, Group 1, and Group 2 Chip Address registers. Table 4 shows the default chip addresses

in I²C Mode.

The signal timings for a read and write cycle are shown in Figure 12 and Figure 13. A Start condition is

defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while

the clock is high. All other transitions of SDA occur while the clock is low.

The first byte sent to the CS3318 after a Start condition consists of a 7-bit chip address field and a R/W

bit (high for a read, low for a write). To communicate with a CS3318, the chip address field should match

either the Individual, Group 1, or Group 2 device address as set by their respective control port registers.

The eighth bit of the address is the R/W bit. If the read/write bit is set high (indicating a read operation)

and the preceding 7 bits do not match its Individual address, the CS3318 will ignore all traffic on the I²C

bus until a Stop and Start condition occurs.

If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register

to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be

output.

There is a MAP auto-increment capability, enabled by the INCR bit (the MSB of the MAP byte). If INCR

is ‘0’, the MAP will stay constant for successive read or writes. If INCR is ‘1’, the MAP will automatically

increment after each byte is written, allowing block writes of successive registers. Each byte is separated

by an acknowledge (ACK) bit. The ACK bit is output from the CS3318 after each input byte is read and is

input to the CS3318 from the microcontroller after each transmitted byte.

AD0 Connection

Default Chip Address

DGND

1000000b

1000001b

Table 4. I²C Mode Default Chip Address

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

SDA

INCR

16 17 18

10 11

13 14 15

27 28

DATA +n

MSB

LSB

Chip Address

Figure 12. Control Port Timing, I²C Write

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