CS3318 datasheet(37/44 Pages) CIRRUS

37 / 44 page

DS693F1

CS3318

7.11

Master 1 Control - Address 12h

7.11.1

Master 1 Mute (Bit 1)

Default = 0

Function:

This bit controls the Master 1 mute state. When set, the Master 1 mute condition is active. When

cleared, the Master 1 mute condition is released.

See “Muting Controls” on page 21 for more information about the muting behavior of the CS3318.

7.11.2

Master 1 ¼ dB Control (Bit 0)

Default = 0

Function:

When set, ¼ dB of gain will be added to the Master 1 volume level.

See Table 6 on page 32 for an example of volume settings using the ¼ dB control.

7.12

Master 2 Mask - Address 13h

Each bit in this register serves as a Master 2 mask for its corresponding channel.

If a mask bit is set to ‘1’, the corresponding channel is unmasked, meaning that it will be affected by the

Master 2 volume and muting controls.

If a mask bit is set to ‘0’, the corresponding channel is masked, meaning that it will not be affected by the

Master 2 volume and muting controls.

This register defaults to FFh (all channels unmasked).

7.13

Master 2 Volume - Address 14h

7.13.1

Master 2 Volume Control (Bits 7:0)

Default = 11010010

Function:

The Master 2 volume control register allows the user to simultaneously gain or attenuate all un-

masked channels from +22 dB to -96 dB in 0.5 dB increments. The volume changes are implemented

as dictated by the ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device

Configuration 2 - Address 0Ch” on page 34).

The value of the Master 2 volume control register is mapped to the desired 0.5 dB step Master 2 vol-

ume setting by the following equation:

432

Reserved

M1_Mute

M1_Qtr

432

M2_Ch8M

M2_Ch7M

M2_Ch6M

M2_Ch5M

M2_Ch4M

M2_Ch3M

M2_Ch2M

M2_Ch1M

432

M2_Vol7

M2_Vol6

M2_Vol5

M2_Vol4

M2_Vol3

M2_Vol2

M2_Vol1

M2_Vol0

Desired Volume Setting in dB

() 210

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