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CS5464 Datasheet(PDF) 31 Page - Cirrus Logic |
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CS5464 Datasheet(HTML) 31 Page - Cirrus Logic |
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31 / 46 page ![]() CS5464 DS682PP1 31 spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD (I2OD) and VOD (V2OD) bits will re-assert themselves even after being cleared, multiple times. LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh- old (PMLO), with respect to AGND pin. For a given part, PMLO can be as low as 2.3 V. LSD bit cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage threshold (PMHI), which is typically 100 mV above the device’s low-voltage threshold. PMHI will never be greater than 2.7 V. FUP Epsilon Updated. Indicates an update to the epsilon value has been placed in the register. IC Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit word that is not recognized as one of the valid commands (see See Section 5.15 Commands on page 24). 6.1.8 Peak Current (Ipeak, I2peak) and Peak Voltage (Vpeak, V2peak) Register Address: 18 (Ipeak), 19 (Vpeak), 22 (I2peak), 23 (V2peak) The Peak Current (Ipeak, I2peak) and Peak Voltage (Vpeak, V2peak) registers contain the instantaneous current and voltage with the greatest magnitude detected during the last computation cycle. The value is represented in two's complement notation and in the range of -1.0 ≤ Ipeak,Vpeak < 1.0 (-1.0 ≤ I2peak,V2peak < 1.0), with the binary point to the right of the MSB. 6.1.9 Apparent Power (S, S2) Register Address: 20 (S), 24 (S2) Apparent power S (S2) is the product of the VRMS and IRMS (V2RMS and I2RMS), The value is represented in unsigned notation and in the range of 0 ≤ S < 1.0 (0 ≤ S2 < 1.0), with the binary point to the right of the MSB. 6.1.10 Power Factor (PF, PF2) Register Address: 21, 25 Power Factor is calculated by dividing the Active (Real) Power by Apparent Power. The value is represented in two's complement notation and in the range of -1.0 ≤ PF < 1.0 (-1.0 ≤ PF2 < 1.0), with the binary point to the right of the MSB. MSB LSB -(20)2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB -(20)2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB -(20)2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 |
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