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IRMCK201 Datasheet(PDF) 8 Page - International Rectifier

Part # IRMCK201
Description  High Performance Configurable Digital AC Servo Control IC
PDF  62 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IRMCK201 Datasheet(HTML) 8 Page - International Rectifier

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IRMCK201
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
8
Detailed Block Diagram
Figure 2 shows a detailed block diagram or the IRMCK201.
All logic and algorithms are pre-programmed, and the
user does not need to make any effort to develop code, alleviating the tedious design process.
If needed, the user can
configure the drive to tailor the control per specific needs to meet the required specification.
This configuration is
easily done by accessing the host register set through the communication interface.
PI
PI
θ
j
e
θ
j
e
Quadrature
Decoding
2/3
dt
+
+
Dea
d
time
Space Vector
PWM
IR2175
interface
IR2175
interface
CLK
BRAKE
FAULT
+
-
-
+
ADS7818
A/D
interface
DC bus dynamic
brake control
I1 x I2
I3
I3
I1
I2
I1 x I2
I3
I3
I1
I2
O
O
I1 x I2
I3
I3
I1
I2
O
0
+
+
PI
6
RAMP
+
-
3
2
DATA
CNVST
MUX
2
Optional
Current Sense
Gate
Signals
3
Encoder
A/B/Z
Encoder
Hall A/B/C
Motor
Phase
Current V
Motor
Phase
Current W
Current
Offset W
Current
Offset V
ID scale
IQ scale
4096
4096
VDLIM
- VDLIM
CURKP
CURKI
- VQLIM
VQLIM
IDREF
INT_REF
Velocity
Control
Enable
Reference
Select
Feedforward
path enable
Slip gain
enable
EncType
Accel Rate
Decel
Rate
4096
Slip gain
IQLIM+
IQLIM-
SPDKP
SPDKI
8 channel
Serial
A/D
Interface
EXT_REF
DCV_FDBK
RS232C/
RS422
Interface
SPI
Slave
Interface
START
STOP
FLTCLR
SYNC
FAULT
PWM ACTIVE
RCV
SND
RTS
CTS
SCK
SDO
SDI
CS
17
Data
Address
Control
Host Register
Interface
Sequence
Control
IQ
ID
IQREF
VD
VQ
VQS
VDS
IV
IW
Parallel
Interface
Configuration
Registers
Monitoring
Registers
MaxEncCount
InitZval
AngleScale
InitZ
Zpol
SpdScale
PWMmode
PWMen
2Pen
GSenseU
GSenseL
ModScl
Dtime
Closed Loop Current Control
Update Rate = PWM carrier frequency x1 or x 2
Closed Loop Velocity Control, Sequencing Control
Update Rate = PWM carrier frequency / 2
Communication Modules
Optional
CurrentSense
VD enable
INT_VD
I1 x I2
I3
I3
I1
I2
O
REF scale
4096
+/-16383 = +/-max_speed
INT_VQ
+/-16383 = +/-4X of rated current for IQ
+/-4095 = +/-rated ID for IM field flux
4ch
DAC module
INT_DAC1
INT_DAC2
INT_DAC3
INT_DAC4
DAC_PWM1
DAC_PWM2
DAC_PWM3
DAC_PWM4
DIR
Figure 2.
Detailed Block Diagram of IRMCK201



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