IRMCK201 datasheet(16/62 Pages) IRF

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IRMCK201

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IIm

plle

nttiin

g tth

e L

w P

s F

Fiilltte

err S

hiie

elld

Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible.

Create the underlining shield by

“copper filling” a larger area in the signal plane of the PCB.

Connect this shield to the LPVSS pin of the IC.

not connect this shield to signal ground (VSS).

p R

p a

d C

s C

ntt V

allu

For a typical FR4 PCB, the values of the passive components are shown in Table 3.

Component

Value

Units

3.9K

Ω

1000

Not Installed

Table 3: PLL Low Pass Filter Values

PLL Reset

There are two reset pins on the IC, XPD and RESETN both low true.

XPD holds the PLL circuitry in reset when

low.

Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input.

The PLL circuit

may take up to 1 ms to become stable.

RESETN asserted low holds the internal DSP logic in reset.

Upon

RESETN going high, the IC digital logic becomes active.

RESETN should be held low during and at least 1 ms after XPD goes high false to hold the internal DSP logic in reset

while the PLL becomes stable.

IRMCK201 Datasheet(PDF) 16 Page - International Rectifier

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