NXP Semiconductors

NTS0102

Dual supply translating transceiver; open-drain; auto direction sensing

dependent upon the output impedance and edge-rate of the external driver. The limits provided for these

parameters in the data sheet assume a driver with output impedance below 50 Ω is used.

13.4 Output load considerations

The maximum lumped capacitive load that can be driven is dependent upon the one-shot pulse duration. In

cases with very heavy capacitive loading, there is a risk that the output will not reach the positive rail within the

one-shot pulse duration.

To avoid excessive capacitive loading, and to ensure correct triggering of the one-shot, it's recommended to

use short trace lengths and low capacitance connectors on NTS0102 PCB layouts. To ensure low impedance

termination and avoid output signal oscillations and one-shot re-triggering, the length of the PCB trace should

be such that the round trip delay of any reflection is within the one-shot pulse duration (approximately 50 ns).

13.5 Power up

During operation VCC(A) must never be higher than VCC(B), however during power-up VCC(A) ≥ VCC(B) does not

damage the device, so either power supply can be ramped up first. There is no special power-up sequencing

required. The NTS0102 includes circuitry that disables all output ports when either VCC(A) or VCC(B) is switched

off.

13.6 Enable and disable

An output enable input (OE) is used to disable the device. Setting OE = LOW

causes all I/Os to assume the high-impedance OFF-state. The disable time (tdis with no external load) indicates

the delay between when OE goes LOW and when outputs actually become disabled. The enable time (ten)

indicates the amount of time the user must allow for one one-shot circuitry to become operational after OE is

taken HIGH. To ensure the high-impedance OFF-state during power-up or power-down, pin OE should be tied

to GND through a pull-down resistor, the minimum value of the resistor is determined by the current-sourcing

capability of the driver.

13.7 Pull-up or pull-down resistors on I/Os lines

Each A port I/O has an internal 10 kΩ pull-up resistor to VCC(A), and each B port I/O has an internal 10 kΩ pull-

up resistor to VCC(B). If a smaller value of pull-up resistor is required, an external resistor must be added parallel

to the internal 10 kΩ, this effects the VOL level. When OE goes LOW the internal pull-ups of the NTS0102 are

disabled.

13.8 GD package vs TL package

Due to differences in package construction the TL package has a center pad vs no center pad for the GD

package. The following section provides guidance in replacement vs new applications.

• No trace under GD package

1. Replacement of GD package: The pad is not electrically connected to the silicon (no wire bond and epoxy

is not conductive) and can be left floating. It is not required to be connected to the PCB. Simply place the

TL package on the same PCB traces as the existing GD package.

NTS0102

All information provided in this document is subject to legal disclaimers.

© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 4.5 — 6 July 2023

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