GS66516T

Top-side cooled 650 V E-mode GaN transistor

Datasheet

Rev 210727

© 2009-2021 GaN Systems Inc.

13

Submit datasheet feedback

Keep out area: Avoid placing traces or vias on the top layer of the PCB, directly

underneath the package. This is to prevent potential electro-migration and solder mask

isolation issues during high temperature or/and voltage operation.

Symmetrical dual gates are provided for flexible layout and easy paralleling. Either gate

drive can be used. If the second gate is not used, it should be left floating.

A separate Source Sense pin is not provided on our top-side products because of the

ultra-low inductance of our GaNPX® packaging. The Source Sense pin functionality can be

implemented simply by routing a Kelvin connection at the side of the Source pad. This

can be done at either side of the source pad for layout optimization.

Do not route vias within the Gate pad as it may affect long term solder joint reliability. For

other pads, it is recommended to implement filled vias for better solder joint reliability.

when the product operates at greater than 100

C it is recommended to also clean the “No-Clean” paste

residues.

Avoid placing printed circuit board traces with high differential voltage to the source or drain directly

underneath the top-cooled package on the PCB to avoid potential electro-migration and solder mask

isolation issues during high temperature or/and voltage operation.

Routing Guidelines

The following layout recommendations are highlighted. Additional detail is provided in Application

Note GN001 at www.gansystems.com.