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HD404458 Datasheet(PDF) 49 Page - Renesas Technology Corp |
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HD404458 Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 122 page  HD404459 Series 47 I/O Pin Type Circuit Pins Peripheral function pins Input pins VCC INT0, etc HLT MIS3 PDR SI, INT 0, INT1, INT 2, INT3, WU 0–WU7, EVNB, EVND Input data STOPC STOPC Notes: 1. In stop mode, the MCU is reset and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes. D Port (D 0–D11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D 0–D9 are input/output pins, and D 10 and D11 are input-only pins. Pins D 0–D9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D 0–D11 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2: $02C–$02E) that are mapped to memory addresses (figure 30). Pin D 11 is multiplexed with peripheral function pin STOPC. The peripheral function mode of this pin is selected by bit 2 (PMRC2) of port mode register C (PMRC: $025) (figure 35). |
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