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HD404458 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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HD404458 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 122 page ![]() HD404459 Series 19 Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT 0 INT 1 Timer D Timer A or INT 2 Timer B or INT 3 Timer C or Serial Wakeup IE 11 11 11 1 IF0 · IM0 10 00 00 0 IF1 · IM1 * 10 00 00 IFTD · IMTD ** 10 00 0 IFTA · IMTA + IF2 · IM2 ** * 10 00 IFTB · IMTB + IF3 · IM3 ** ** 10 0 IFTC · IMTC + IFS · IMS ** ** * 10 IFWU · IMWU ** ** ** 1 Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 12 3 4 5 6 Instruction execution* IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Stacking Figure 9 Interrupt Processing Sequence |
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