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CS5535 Datasheet(PDF) 391 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 391 Page - National Semiconductor (TI) |
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391 / 555 page  Revision 0.8 391 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.9 Bank 6 Register Descriptions The bit formats for the registers in Bank 6 are summarized in Table 5-44. Detailed descriptions of each register follow. 5.12.9.1 IR Control Register 3 (IRCR3) IRCR3 is used to select the operating mode of the Sharp-IR interface. Table 5-44. Bank 6 Bit Map Register Bits I/O Offset Name 7 6 5 4 3210 00h IRCR3 SHDM_DS SHMD_DS RSVD 01h RSVD RSVD 02h SIR_PW RSVD SPW3 SPW2 SPW1 SPW0 03h BSR BKSE BSR[6:0] 04h-07h RSVD RSVD I/O Offset 00h Type R/W Reset Value 20h IRCR3 Register Map 76 54 32 10 SHDM_DS SHMD_DS RSVD IRCR3 Bit Descriptions Bit Name Description 7 SHDM_DS Sharp-IR Demodulation Disable. 0: Internal 500 kHz receiver demodulation enabled (Default). 1: Internal demodulation disabled. 6 SHMD_DS Sharp-IR Modulation Disable. 0: Internal 500 kHz transmitter modulation enabled (Default). 1: Internal modulation disabled. 5:0 RSVD Reserved. Read as written. |
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