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CS5535 Datasheet(PDF) 393 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 393 Page - National Semiconductor (TI) |
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393 / 555 page  Revision 0.8 393 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.10 Bank 7 Register Descriptions The bit formats for the registers in Bank 7 are summarized in Table 5-44. Detailed descriptions of each register follow. The CEIR utilizes two carrier frequency ranges (See Table 5-50 on page 395): • Low range - spans from 30 kHz to 56 kHz, in 1 kHz increments. • High range - includes three frequencies: 400 kHz, 450 kHz or 480 kHz. High and low frequencies are specified independently to allow separate transmission and reception modulation settings. The transmitter uses the carrier frequency settings in Table 5-50 "CEIR Carrier Frequency Encoding" on page 395. The two registers at I/O Offsets 04h and 07h (IR transceiver configuration registers) are provided to configure the virtual IR dongle interface via IRSL[2:0] bits (to allow legacy software writes on these bits). 5.12.10.1 IR Receiver Demodulator Control Register (IRRXDC) IRRXDC controls settings for Sharp-IR and CEIR reception. After reset, the content of this register is 29h. This setting selects a subcarrier frequency in a range between 34.61 kHz and 38.26 kHz for the CEIR mode, and from 480.0 kHz to 533.3 kHz for the Sharp-IR mode. The value of this register is ignored if the receiver demodulation for both modes is dis- abled (see bit 7 (SHDM_DS) in Section 5.12.9.1 "IR Control Register 3 (IRCR3)" on page 391 and bit 4 (RCDM_DS) in Section 5.12.10.3 "CEIR Configuration Register (RCCFG)" on page 396). The available frequency ranges for CEIR and Sharp-IR modes are given in Tables 5-46 through 5-48. Table 5-45. Bank 7 Bit Map Register Bits I/O Offset Name 7 654 32 1 0 00h IRRXDC DBW[2:0] DFR[4:0] 01h IRTXMC MCPW[2:0] MCFR[4:0] 02h RCCFG R_LEN T_OV RXHSC RCDM_DS RSVD TXHSC RC_MMD[1:0] 03h BSR BKSE BSR[6:0] 04h IRCFG1 STRV_MS RSVD SET_IRTX IRRX1_LV RSVD IRIC[2:0] 05h-06h RSVD RSVD 07h IRCFG4 RSVD IRSL0_DS RXINV IRSL21_DS RSVD I/O Offset 00h Type R/W Reset Value 29h IRRXDC Register Map 76 54 32 10 DBW[2:0] DFR[4:0] IRRXDC Bit Descriptions Bit Name Description 7:5 DBW[2:0] Demodulator Bandwidth. These bits set the demodulator bandwidth for the selected frequency range. The subcarrier signal frequency must fall within the specified frequency range in order to be accepted. Used for both Sharp-IR and CEIR modes. (Default = 001.) 4:0 DFR[4:0] Demodulator Frequency. These bits select the subcarrier’s center frequency for the CEIR mode. (Default = 01001.) |
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