CS5535 datasheet(397/555 Pages) NSC

397 / 555 page

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UART/IR Controller Register Descriptions (Continued)

5.12.10.4 Bank Select Register (BSR)

BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis-

ters" on page 373 for bit descriptions.

RCDM_DS

Receiver Demodulation Disable. When this bit is 1, the internal demodulator is dis-

abled. The internal demodulator, when enabled, performs carrier frequency checking and

envelope generation. This bit must be set to 1 (disabled) when the demodulation is per-

formed externally, or when oversampling mode is selected to determine the carrier fre-

quency.

RSVD

Reserved. Write as 0.

TXHSC

Transmitter Subcarrier Frequency Select. This bit selects the modulation carrier fre-

quency range.

0: Low frequency: 30.0-56.9 kHz.

1: High frequency: 400-480 kHz.

1:0

RC_MMD[1:0]

Transmitter Modulator Mode. Determines how IR pulses are generated from the trans-

mitted bit string.

00: C_PLS modulation mode. Pulses are generated continuously for the entire logic 0 bit

time.

01: 8_PLS modulation mode. 8 pulses are generated each time one or more logic 0 bits

are transmitted following a logic 1 bit.

10: 6_PLS Modulation Mode. 6 pulses are generated each time one or more logic 0 bits

are transmitted following a logic 1 bit.

11: Reserved. Result is indeterminate.

I/O Offset

03h

Type

R/W

Reset Value

00h

RCCFG Bit Descriptions

Bit

Name

Description

CS5535 Datasheet(PDF) 397 Page - National Semiconductor (TI)