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CS5535 Datasheet(PDF) 401 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 401 Page - National Semiconductor (TI)

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Revision 0.8
401
www.national.com
DMA Register Descriptions (Continued)
006h
R/W
8
Slave DMA Channel 3 Memory Address
(DMA_CH3_ADDR_BYTE)
xxh
Page 405
007h
R/W
8
Slave DMA Channel 3 Transfer Count
(DMA_CH3_CNT_BYTE)
xxh
Page 406
008h
R
8
Slave DMA Channel [3:0] Status
(DMA_CH3:0_STS)
00h
Page 406
W
8
Slave DMA Channel [3:0] Command
(DMA_CH3:0_CMD)
xxh
Page 407
009h
WO
8
Slave DMA Channel [3:0] Software Request
(DMA_CH3:0_SFT_REQ)
xxh
Page 407
00Ah
WO
8
Slave DMA Channel [3:0] Channel Mask
(DMA_CH3:0_CHMSK)
xxh
Page 407
00Bh
WO
8
Slave DMA Channel [3:0] Mode
(DMA_CH3:0_MODE)
xxh
Page 408
00Ch
WO
8
Slave DMA Channel [3:0] Clear Byte Pointer
(DMA_CH3:0_CLR_PNTR)
xxh
Page 408
00Dh
WO
8
Slave DMA Channel [3:0] Master Clear
(DMA_CH3:0_MSTR_CLR)
xxh
Page 409
00Eh
WO
8
Slave DMA Channel [3:0] Clear Mask Register
(DMA_CH3:0_CLR_MSK)
xxh
Page 409
00Fh
WO
8
Slave DMA Channel [3:0] Write Mask Register
(DMA_CH3:0_WR_MSK)
0Fh
Page 409
0C0h
R/W
8
Master DMA Channel 4 Memory Address
(DMA_CH4_ADDR_BYTE)
xxh
Page 410
0C2h
R/W
8
Master DMA Channel 4 Transfer Count
(DMA_CH4_CNT_BYTE)
xxh
Page 410
0C4h
R/W
8
Master DMA Channel 5 Memory Address
(DMA_CH5_ADDR_BYTE)
xxh
Page 410
0C6h
R/W
8
Master DMA Channel 5 Transfer Count
(DMA_CH5_CNT_BYTE)
xxh
Page 410
0C8h
R/W
8
Master DMA Channel 6 Memory Address
(DMA_CH6_ADDR_BYTE)
xxh
Page 410
0CAh
R/W
8
Master DMA Channel 6 Transfer Count
(DMA_CH6_CNT_BYTE)
xxh
Page 410
0CCh
R/W
8
Master DMA Channel 7 Memory Address
(DMA_CH7_ADDR_BYTE)
xxh
Page 410
0CEh
R/W
8
Master DMA Channel 7 Transfer Count
(DMA_CH7_CNT_BYTE)
xxh
Page 410
0D0h
R
8
Master DMA Channel [7:4] Status
(DMA_CH7:4_STS)
00h
Page 411
W
8
Master DMA Channel [7:4] Command
(DMA_CH7:4_CMD)
xxh
Page 411
0D2h
WO
8
Master DMA Channel [7:4] Software Request
(DMA_CH7:4_SFT_REQ)
xxh
Page 412
0D4h
WO
8
Master DMA Channel [7:4] Channel Mask
(DMA_CH7:4_CHMSK)
xxh
Page 412
Table 5-53. DMA Native Registers Summary (Continued)
I/O Address
Type
Width
(Bits)
Register Name
Reset Value
Reference



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