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CS5535 Datasheet(PDF) 460 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 460 Page - National Semiconductor (TI) |
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460 / 555 page ![]() www.national.com 460 Revision 0.8 GPIO Subsystem Register Descriptions (Continued) 5.16.3.6 GPIO Event Counter Decrement (GPIO[x]_EVNTCNT_DEC) There are two 32-bit Event Counter Decrement registers one for the lower bank (GPIO[15:0]) and one for the higher bank (GPIO[31:16]) of GPIOs.These registers generate one 33 ns wide pulse when written to it, so multiple successive writes may be performed without waiting for the previous write to ‘complete; in addition, reading these registers always provides 0s. GPIO Low Bank Event Counter Decrement (GPIOL_EVNTCNT_DEC) GPIO I/O Offset F8h Type R/W Reset Value 00000000h GPIOL_EVNTCNT_DEC Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 RSVD GPIOL_EVNTCNT_DEC Bit Descriptions Bit Name Description 31:16 RSVD Reserved. Write/read as 0. 15 ECD15 GPIO15 Event Counter Decrement. Writing this bit high generates a decrement pulse to the event counter that has been associated with this GPIO. There is no need to write the bit low again. This bit will always read as low. Event counters are associated with specific GPIOs via the GPIO_FE[x]_SEL register set. 14 ECD14 GPIO14 Event Counter Decrement. Same as EDC15 (bit 15) 13 ECD13 GPIO13 Event Counter Decrement. Same as EDC15 (bit 15) 12 ECD12 GPIO12 Event Counter Decrement. Same as EDC15 (bit 15). 11 ECD11 GPIO11 Event Counter Decrement. Same as EDC15 (bit 15). 10 ECD10 GPIO10 Event Counter Decrement. Same as EDC15 (bit 15). 9 ECD9 GPIO9 Event Counter Decrement. Same as EDC15 (bit 15). 8 ECD8 GPIO8 Event Counter Decrement. Same as EDC15 (bit 15). 7 ECD7 GPIO7 Event Counter Decrement. Same as EDC15 (bit 15). 6 ECD6 GPIO6 Event Counter Decrement. Same as EDC15 (bit 15). 5 ECD5 GPIO5 Event Counter Decrement. Same as EDC15 (bit 15). 4 ECD4 GPIO4 Event Counter Decrement. Same as EDC15 (bit 15). 3 ECD3 GPIO3 Event Counter Decrement. Same as EDC15 (bit 15). 2 ECD2 GPIO2 Event Counter Decrement. Same as EDC15 (bit 15). 1 ECD1 GPIO1 Event Counter Decrement. Same as EDC15 (bit 15). 0 ECD0 GPIO0 Event Counter Decrement. Same as EDC15 (bit 15). |
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