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CS5535 Datasheet(PDF) 513 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 513 Page - National Semiconductor (TI) |
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513 / 555 page  Revision 0.8 513 www.national.com 5.20 GEODELINK CONTROL PROCESSOR REGISTER DESCRIPTIONS The GeodeLink Control Processor’s (GLPC) register set consists of: • Standard GeodeLink Device MSRs • GLCP Specific MSRs The MSRs (both Standard and GLPC Specific) are accessed via the RDMSR and WRMSR processor instruc- tions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. The tables that follow are register summary tables that include reset values and page references where the bit descriptions are provided. Table 5-71. Standard GeodeLink Device MSRs Summary MSR Address Type Register Reset Value Reference 51700000h RO GeodeLink Device Capabilities MSR (GLCP_GLD_MSR_CAP) 00000000_002021xxh Page 514 51700001h R/W GeodeLink Device Master Configuration MSR (GLCP_GLD_MSR_CONFIG) 00000000_00000000h Page 514 51700002h R/W GeodeLink Device SMI MSR (GLCP_GLD_MSR_SMI) 00000000_00000003h Page 515 51700003h R/W GeodeLink Device Error MSR (GLCP_GLD_MSR_ERROR) 00000000_00000000h Page 515 51700004h R/W GeodeLink Device Power Management MSR (GLCP_GLD_MSR_PM) 00000000_00000000h Page 516 51700005h R/W GeodeLink Device Diagnostic MSR (GLCP_GLD_MSR_DIAG) 00000000_00000000h Page 517 Table 5-72. GLPC Specific MSRs Summary MSR Address Type Register Reset Value Reference 51700008h R/W GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY) 00000000_00000000h Page 519 51700009h R/W GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE) 00000000_00000000h Page 519 5170000Ah RO GLCP Fabrication (GLCP_FAB) 00000000_00000002h Page 520 5170000Bh R/W GLCP Global Power Management Control (GLCP_GLB_PM) 00000000_00000000h Page 520 5170000Ch R/W GLCP Debug Output from Chip (GLCP_DBGOUT) 00000000_00000000h Page 520 5170000Dh R/W Reserved Registers (GLPC_RSVD) 00000000_00000000h --- 5170000Eh R/W Software Communication Register (GLCP_DOWSER) 00000000_00000000h Page 521 5170000Fh R/W GLCP Reserved Register (GLPC_RSVD) 00000000_00000000h --- 51700010h R/W GLCP Clock Control (GLCP_CLKOFF) 00000000_00000000h Page 521 51700011h RO GLCP Clock Active (GLCP_CLKACTIVE) 0000000x_xxxxxxxxxh Page 521 51700012h R/W GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE) 00000000_00000000h Page 522 51700013h R/W GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK) 00000000_00000000h Page 522 51700014h R/W GLCP System Reset Control (GLCP_SYS_RST) 00000000_00000000h Page 523 51700015h R/W Reserved Registers (GLPC_RSVD) 00000000_00000000h --- 51700016h R/W GLCP Debug Clock Control (GLCP_DBGCLKCTL) 00000000_00000002h Page 524 51700017h RO Chip Revision ID (GLCP_CHIP_REV_ID) 00000000_000000xxh Page 524 |
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