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CS5535 Datasheet(PDF) 509 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 509 Page - National Semiconductor (TI) |
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509 / 555 page  Revision 0.8 509 www.national.com Flash Controller Register Descriptions (Continued) 5.19.2.4 NAND Status (NAND_STS) 5.19.2.5 NAND ECC Control (NAND_ECC_CTL) Flash Memory Offset 810h Flash I/O Offset 06h Type R/W Reset Value 0xh NAND_STS Register Map 76543 210 RSVD FLASH_RDY CTLR_BUSY CMD_COMP DIST_ST NAND_STS Bit Descriptions Bit Name Description 7:4 RSVD (RO) Reserved (Read Only). Returns 0 when read. 3FLASH_RDY (RO) Flash Ready (Read Only). Double synchronized output (with respect to local bus clock) of the NAND Flash device’s RDY/BUSY#. 2 CTLR_BUSY (RO) NAND Controller Busy (Read Only). When high, indicates that the NAND Controller’s state machines are busy. 1CMD_COMP NAND Command Complete. When high, indicates that the most recent NAND com- mand has completed. May be read anytime. Write 1 to clear this bit. Writing 0 has no effect. 0DIST_ST NAND Distract Status. Occurrence of a NOR interruption during a NAND transaction sets this bit. Write 1 to clear this bit. Writing 0 has no effect. A NAND transaction is started as soon as CE# goes low. It is stopped when CE# goes high. Typically, a NAND transaction needs multiple software commands (from 6 to ~500). Since the Flash Interface is shared between NAND and NOR Flash Controllers and the NOR Flash Controller gets priority to use the Flash Interface, a NAND transac- tion may be interrupted by a NOR transaction. DIST_ST bit is set to record this event. NAND Flash software must take necessary actions to recover the uncompleted trans- action. Flash Memory Offset 815h Flash I/O Offset 08h Type R/W Reset Value 04h NAND_ECC_CTL Register Map 76543 210 RSVD PARITY CLRECC ENECC NAND_ECC_CTL Bit Descriptions Bit Name Description 7:3 RSVD Reserved. Reads return value written. |
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